我想检查我的工作和对管道的理解，不幸的是，火星不适合此功能，因此很难验证我的假设。
我将说明放在电子表格中，以帮助我了解发生了什么，我想确保这是正确的。我使用蓝色指示周期中的每个阶段，与书不同，我没有表示每个阶段发生的一半（即上半场，下半场是ID）
根据Patterson和Hennessey的这本书，ID阶段在WB开始时就发生了。
，这应该意味着最后一个SW命令应按预期工作，因为先前（有效指令）的WB发生在该周期的开始时 - ID在尾部。
I would like to check my work and understanding of pipelines, unfortunately MARS doesn't accommodate this feature so it is hard to verify my hypothesis.
I placed the instructions in a spreadsheet to help me understand what is going on and I would like to ensure that this is correct. I used the color blue to indicate each stage in the cycle, unlike the book, I didn't denote which half of the cycle each stage occurs (I.E WB is in the first half and ID in the second half)
Based on the book by Patterson and Hennessey, the ID stage occurs towards the end while WB is at the start.
So that should mean that the last SW command should work as intended because the WB of the prior (valid instruction) occurs at the start of that cycle - while ID is at the tail.
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是的，看起来正确。
后续指令的ID阶段可以与上述指令的WB阶段重叠，并且仍然获得适当的价值。
这是因为，对于WB中的一个，新数据已完全准备在周期的开始时进入寄存器 - 没有什么可计算的。完整的答案已在上一循环结束时完全计算出来，因此不需要更改书面记录的值。＆nbsp; 计算输出之前，在先前周期中遵循实质逻辑的输入。
（与Alu操作进行比较，在 要解决以包括在同一周期中发生的新书面的WB值，否则设计人员将在寄存器文件中放置内部旁路/向前。＆nbsp;无论哪种方式，ID阶段都将在同一周期而不是先前的陈旧值中获得书面寄存器（WB）的最新值。
他们所说的是，WB发生在周期的上半年，ID发生在下半年。＆nbsp;但是，它实际上是在内部与各种处理器实现的 - 想法是，我们可以依靠在同一周期中编写的读取值。＆nbsp; 周期分为一半，但这是另一种实现的可能性。）
（我相信他们没有说明他们是否建议使用时钟的另一个过渡（例如向下边缘）将 ：
图4.52上的标题，以及
从图4.52。＆nbsp;这些相同的文本发生在本书的RISC V版本中（尽管相对于图号4.50而不是4.52）。
我们还要注意，引入转发（又称绕过）以减轻危害（而不是程序员插入
nops）时，需要从ex-＆gt; ex以及mem-＆gt中转发。例如＆nbsp;第一个是Alu背靠背的原始危害，第二个是用于使用负载的原始危害（背对背）以及通过1个指令分开的Alu危害！Yes, that looks correct.
The ID stage of a succeeding instruction can overlap with the WB stage of a preceding instruction, and still get the proper value.
This is because, for one in WB, the new data is fully ready to go into the registers at the very start of the cycle — there is nothing to compute; the complete answers have been fully computed by the end of the prior cycle, so no bits need change in the values being recorded by the write back. (Compare with ALU operation where substantial logic follows input from the prior cycle, before outputs can be computed.)
In the ID stage, the values are looked up in the register file, and either the cycle timing will be sufficiently long to allow the values to settle to include newly written WB values that happen in the same cycle, or else the designers will put an internal bypass/forward inside the register file. Either way, the ID stage will obtain the latest value of a register that is written (WB) in the same cycle rather than a prior stale value.
The way they have put it is that WB happens in the first half of the cycle and ID happens in the second half. However it is actually implemented internally to various processors — the idea is that we can count on reading values written in the same cycle. (I believe they leave it unsaid as to whether they are suggesting to use the other transition of the clock (e.g. the downward edge) to physically divide the cycle in half or not, but that is another implementation possibility.)
From the same text book:
Caption on Figure 4.52, and,
From main text just above the Figure 4.52. These same texts occurs in the RISC V version of the book (though relative to Figure number 4.50 instead of 4.52).
Let's also note that when forwarding (aka bypassing) is introduced to mitigate hazards (instead of programmer inserting
nops), there will need to be forwarding from EX->EX as well as MEM->EX. The first is for back to back RAW hazards on the ALU, where the second is for both load-use RAW hazards (back to back) as well as ALU hazards that are separated by 1 instruction!