SUN E450 不能启动（含串口）

发布于 2022-09-04 15:32:34 字数 21565 浏览 20 评论 5

启动到最下面就不走了。键盘无反应。好像死机。

Software Power ON

CPU1 has assumed the role of Boot CPU

1>
1>@(#) Sun UltraSPARC-II 4-way UPA/PCI POST 6.1.0 12/20/00: 16:32
1>INFO: Processor 1 is master CPU.
1>INFO: Motherboard rev FCS
1>
1> <00> Init System BSS
1> <00> NVRAM Battery Detect Test
1> <00> NVRAM Scratch Addr Test
1> <00> DMMU TLB Tag Access Test
1> <00> DMMU TLB RAM Access Test
1> <00> Probe Ecache
1>INFO: 8192KB Ecache
1> <00> Ecache RAM Addr Test
1> <00> Ecache Tag Addr Test
1> <00> Invalidate Ecache Tags
1> <00> SC Dtag Probe
1>INFO: Dtag supports up to 8MB Ecache
1>INFO: Processor 0 is missing or disabled.
1>INFO: Processor 2 is missing or disabled.
1>INFO: Processor 3 - UltraSPARC-II.
1> <00> Init SC Regs
1> <00> SC Address Reg Test
1> <00> SC Reg Index Test
1> <00> SC Regs Test
1> <00> SC Dtag RAM Addr Test
1> <00> SC Dtag Init
1> <00> Init SC Regs
1> <00> SC Cache Size Init
3> <00> Probe Ecache
3>INFO: 8192KB Ecache
3> <00> Ecache RAM Addr Test
3> <00> Ecache Tag Addr Test
3> <00> Invalidate Ecache Tags
1> <00> Synch up Processor Ecache Sizes
3> <00> Synch up Processor Ecache Sizes
1> <00> Probe Memory
1>INFO: 1024MB Bank 0
1>INFO: 1024MB Bank 1
1>INFO: No memory detected in Bank 2
1>INFO: No memory detected in Bank 3
1> <00> Test Memory Data Lines
1> <00> Test Memory Address Lines
1> <00> Malloc Post Memory
1> <00> Init Post Memory
1> <00> Map PROM/STACK/NVRAM in DMMU
1> <00> Memory Stack Test
1> <00> Init Memory
1> <00> ECC Memory Addr Test
3> <00> DMMU TLB Tag Access Test
3> <00> DMMU TLB RAM Access Test
3> <00> Map PROM/STACK/NVRAM in DMMU
3> <00> Update Slave Stack/Frame Ptrs
3> <00> Memory Data Lines
3> <00> Memory Address Lines
1> <00> V9 Instruction Test
3> <00> V9 Instruction Test
1> <00> Memory Addr w/ Ecache Test
1> <00> Block Memory Addr Test
1> <00> FPU Regs Test
1> <00> FPU Move Regs Test
1> <00> FPU State Reg Test
1> <00> FPU Functional Test
1> <00> FPU Trap Test
1> <00> DMMU Primary Context Reg Test
1> <00> DMMU Secondary Context Reg Test
1> <00> DMMU TSB Reg Test
1> <00> DMMU Tag Access Reg Test
1> <00> DMMU VA Watchpoint Reg Test
1> <00> DMMU PA Watchpoint Reg Test
1> <00> IMMU TSB Reg Test
1> <00> IMMU Tag Access Reg Test
1> <00> IMMU TLB RAM Access Test
1> <00> IMMU TLB Tag Access Test
1> <00> Dcache RAM Test
1> <00> Dcache Tag Test
1> <00> Icache RAM Test
1> <00> Icache Tag Test
1> <00> Icache Next Test
1> <00> Icache Predecode Test
1> <00> DMMU Hit/Miss Test
1> <00> DMMU Little Endian Test
1> <00> IU ASI Access Test
1> <00> FPU ASI Access Test
3> <00> FPU Regs Test
3> <00> FPU Move Regs Test
3> <00> FPU State Reg Test
3> <00> FPU Functional Test
3> <00> FPU Trap Test
3> <00> DMMU Primary Context Reg Test
3> <00> DMMU Secondary Context Reg Test
3> <00> DMMU TSB Reg Test
3> <00> DMMU Tag Access Reg Test
3> <00> DMMU VA Watchpoint Reg Test
3> <00> DMMU PA Watchpoint Reg Test
3> <00> IMMU TSB Reg Test
3> <00> IMMU Tag Access Reg Test
3> <00> IMMU TLB RAM Access Test
3> <00> IMMU TLB Tag Access Test
3> <00> Dcache RAM Test
3> <00> Dcache Tag Test
3> <00> Icache RAM Test
3> <00> Icache Tag Test
3> <00> Icache Next Test
3> <00> Icache Predecode Test
3> <00> DMMU Hit/Miss Test
3> <00> DMMU Little Endian Test
3> <00> IU ASI Access Test
3> <00> FPU ASI Access Test
1> <00> CPU Addr Align Trap Test
1> <00> DMMU Access Priv Page Test
1> <00> DMMU Write Protected Page Test
1> <00> Copy Post to Memory
1> <00> Map/Exec POST from Memory
1> <00> Map alternate CPUs
1> <00> Init Memory
1>INFO: 1024MB Bank 0
1>INFO: 1024MB Bank 1
1>INFO: No memory in Bank 2
1>INFO: No memory in Bank 3
1> <00> OBP Memory Test
1> <1f> Init Psycho
1> <1f> Psycho Cntl and UPA Reg Test
1> <1f> Psycho DMA Scoreboard Reg Test
1> <1f> Psycho Perf Cntl Reg Test
1> <1f> PIO Decoder and BCT Test
1> <1f> PCI Byte Enable Test
1> <1f> Counter/Timer Limit Regs Test
1> <1f> Timer Increment Test
1> <1f> Timer Reload Test
1> <1f> Timer Periodic Test
1> <1f> Mondo Int Map (short) Reg Test
1> <1f> Mondo Int Set/Clr Reg Test
1> <1f> Psycho IOMMU Regs Test
1> <1f> Psycho IOMMU RAM NTA Test
1> <1f> Psycho IOMMU CAM NTA Test
1> <1f> Psycho IOMMU RAM Address Test
1> <1f> Psycho IOMMU CAM Address Test
1> <1f> IOMMU TLB Compare Test
1> <1f> IOMMU TLB Flush Test
1> <1f> Stream Buff A Control Reg Test
1> <1f> Psycho ScacheA Page Tag Addr Test
1> <1f> Psycho ScacheA Line Tag Addr Test
1> <1f> Psycho ScacheA RAM Addr Test
1> <1f> Psycho ScacheA Page Tag NTA Test
1> <1f> Psycho ScacheA Line Tag NTA Test
1> <1f> Psycho ScacheA Err Status NTA Test
1> <1f> Psycho ScacheA RAM NTA Test
1> <1f> Stream Buff B Control Reg Test
1> <1f> Psycho ScacheB Page Tag Addr Test
1> <1f> Psycho ScacheB Line Tag Addr Test
1> <1f> Psycho ScacheB RAM Addr Test
1> <1f> Psycho ScacheB Page Tag NTA Test
1> <1f> Psycho ScacheB Line Tag NTA Test
1> <1f> Psycho ScacheB Err Status NTA Test
1> <1f> Psycho ScacheB RAM NTA Test
1> <1f> PBMA PCI Config Space Regs Test
1> <1f> PBMA Control/Status Reg Test
1> <1f> PBMA Diag Reg Test
1> <1f> PBMB PCI Config Space Regs Test
1> <1f> PBMB Control/Status Reg Test
1> <1f> PBMB Diag Reg Test
1> <1f> Consist DMA Rd, IOMMU miss Lpbk Test
1> <04> Init Psycho
1> <04> Psycho Cntl and UPA Reg Test
1> <04> Psycho DMA Scoreboard Reg Test
1> <04> Psycho Perf Cntl Reg Test
1> <04> PIO Decoder and BCT Test
1> <04> PCI Byte Enable Test
1> <04> PBMA PCI Config Space Regs Test
1> <04> PBMA Control/Status Reg Test
1> <04> PBMA Diag Reg Test
1> <04> PBMB PCI Config Space Regs Test
1> <04> PBMB Diag Reg Test
1> <04> Consist DMA Rd, IOMMU miss Lpbk, PCI B Bus Test
1> <04> Consist DMA Rd, IOMMU miss Lpbk Test
1> <06> Init Psycho
1> <06> Psycho Cntl and UPA Reg Test
1> <06> Psycho DMA Scoreboard Reg Test
1> <06> Psycho Perf Cntl Reg Test
1> <06> PIO Decoder and BCT Test
1> <06> PCI Byte Enable Test
1> <06> PBMA PCI Config Space Regs Test
1> <06> PBMA Control/Status Reg Test
1> <06> PBMA Diag Reg Test
1> <06> PBMB PCI Config Space Regs Test
1> <06> PBMB Diag Reg Test
1> <06> Consist DMA Rd, IOMMU miss Lpbk, PCI B Bus Test
1> <06> Consist DMA Rd, IOMMU miss Lpbk Test
1> <1f> Init Psycho
1> <1f> Mondo Generate Interrupt Test
1> <1f> Timer Interrupt Test
1> <1f> Timer Interrupt w/ periodic Test
1> <1f> Psycho Stream Buff A Flush Sync Test
1> <1f> Psycho Stream Buff B Flush Sync Test
1> <1f> Psycho Stream Buff A Flush Invalidate Test
1> <1f> Psycho Stream Buff B Flush Invalidate Test
1> <1f> Psycho Merge Buffer w/ Scache A Test
1> <1f> Psycho Merge Buffer w/ Scache B Test
1> <1f> Consist DMA Rd, IOMMU miss Ebus Test
1> <1f> Consist DMA Rd, IOMMU miss Lpbk Test
1> <1f> Consist DMA Rd, IOMMU hit Ebus Test
1> <1f> Consist DMA Rd, IOMMU hit Lpbk Test
1> <1f> Consist DMA Wr, IOMMU miss Ebus Test
1> <1f> Consist DMA Wr, IOMMU miss Lpbk Test
1> <1f> Consist DMA Wr, IOMMU hit Ebus Test
1> <1f> Consist DMA Wr, IOMMU hit Lpbk Test
1> <04> Init Psycho
1> <04> Psycho Stream Buff A Flush Sync Test
1> <04> Psycho Stream Buff B Flush Sync Test
1> <04> Psycho Stream Buff A Flush Invalidate Test
1> <04> Psycho Stream Buff B Flush Invalidate Test
1> <04> Psycho Merge Buffer w/ Scache A Test
1> <04> Psycho Merge Buffer w/ Scache B Test
1> <04> Consist DMA Rd, IOMMU miss Lpbk Test
1> <04> Consist DMA Rd, IOMMU miss Lpbk, PCI B Bus Test
1> <04> Consist DMA Rd, IOMMU hit Lpbk Test
1> <04> Consist DMA Wr, IOMMU miss Lpbk Test
1> <04> Consist DMA Wr, IOMMU hit Lpbk Test
1> <06> Init Psycho
1> <06> Psycho Stream Buff A Flush Sync Test
1> <06> Psycho Stream Buff B Flush Sync Test
1> <06> Psycho Stream Buff A Flush Invalidate Test
1> <06> Psycho Stream Buff B Flush Invalidate Test
1> <06> Psycho Merge Buffer w/ Scache A Test
1> <06> Psycho Merge Buffer w/ Scache B Test
1> <06> Consist DMA Rd, IOMMU miss Lpbk Test
1> <06> Consist DMA Rd, IOMMU miss Lpbk, PCI B Bus Test
1> <06> Consist DMA Rd, IOMMU hit Lpbk Test
1> <06> Consist DMA Wr, IOMMU miss Lpbk Test
1> <06> Consist DMA Wr, IOMMU hit Lpbk Test
1> <1f> Init Psycho
1> <1f> PIO Read Err, Master Abort Test
1> <1f> PIO Read Err, Target Abort Test
1> <1f> PIO Write Err, Master Abort Test
1> <1f> PIO Write Err, Target Abort Test
1> <1f> Pri CE ECC Err Test
1> <1f> Pri UE ECC Err Test
1> <1f> Pri 2 bit w/ bit hole UE ECC Err Test
1> <1f> Pri 3 bit UE ECC Err Test
1> <04> Init Psycho
1> <04> PIO Read Err, Master Abort Test
1> <04> PIO Read Err, Target Abort Test
1> <04> PIO Write Err, Master Abort Test
1> <04> PIO Write Err, Target Abort Test
1> <04> Pri CE ECC Err Test
1> <04> Pri UE ECC Err Test
1> <04> Pri 2 bit w/ bit hole UE ECC Err Test
1> <04> Pri 3 bit UE ECC Err Test
1> <06> Init Psycho
1> <06> PIO Read Err, Master Abort Test
1> <06> PIO Read Err, Target Abort Test
1> <06> PIO Write Err, Master Abort Test
1> <06> PIO Write Err, Target Abort Test
1> <06> Pri CE ECC Err Test
1> <06> Pri UE ECC Err Test
1> <06> Pri 2 bit w/ bit hole UE ECC Err Test
1> <06> Pri 3 bit UE ECC Err Test
1>STATUS=PASSED

Power On Selftest Completed
Status = 0000.0000.0000.0000 ffff.ffff.f00b.4b60 ffdf.ffff.0bd1.1111
POST Reset

CPU1 has assumed the role of Boot CPU

@(#) Sun Ultra 450  3.22 Version 0 created 2000/12/20 16:31
Offline: CPU0 (MD'ed)
Online:  CPU1  Ultra-II (v1.0) 5:1 8192KB 2-2 ECache MCap 10
Offline: CPU2 (MD'ed)
Online:  CPU3  Ultra-II (v1.0) 5:1 8192KB 2-2 ECache MCap 10
Motherboard DTAG SRAMs support up to 8192KB of ECache per CPU Module
Setting system ECache size to 8192KB
Clearing DTAGS...Done
Auxio Level = 0000.0000.0000.0005
Clearing E-Cache Tags...Done
Clearing I/D TLBs...Done
Probing Memory...Done
HiMem base = 0000.0000.0000.0000 size = 0000.0000.8000.0000
Clearing Memory...including Unix Retained Memory...Done
MMUs ON
Copying ROM to RAM...Done
RAM CRC = 0000.0000.adff.802f;  ROM CRC = 0000.0000.adff.802f
Decompressing into Memory...0000.0000.0004.4c04 (276KB)...Done
Size = 0000.0000.0008.49e0 (531KB)
Starting Forth kernel at 0000.0000.f005.9d3c
ttya initialized
Memory in 2 - way interleave configuration
...Bank #0 256 + 256 + 256 + 256 : 1024 MB
...Bank #1 256 + 256 + 256 + 256 : 1024 MB [Available 2048MB @ 0 ]
...Bank #2 0 + 0 + 0 + 0 : 0 MB [Not In Use]
...Bank #3 0 + 0 + 0 + 0 : 0 MB [Not In Use]
Programming memory controller for 10ns/100MHz UPA timing
Environmental monitor: enabled
Probing Floppy: drive detected on ID0
Probing Audio: audio codec not present
Primary UPA probing
Probing all UPA slots ................................Done.
At UPA Slot  1 Created Node(s)...SUNW,UltraSPARC-II
At UPA Slot  3 Created Node(s)...SUNW,UltraSPARC-II
At UPA Slot  4 Created Node(s)...pci pci
At UPA Slot  6 Created Node(s)...pci pci
At UPA Slot 1f Created Node(s)...pci pci

Primary I/O probing
Probing /pci@1f,4000 at Device 1  network
Probing /pci@1f,4000 at Device 3  scsi disk tape
Probing /pci@1f,4000 at Device 2  scsi disk tape
Probing /pci@1f,4000 at Device 4  Nothing there
Probing /pci@1f,2000 at Device 0  This slot excluded from probing...
Probing /pci@1f,2000 at Device 1  Nothing there
Probing /pci@1f,2000 at Device 2  Nothing there
Probing /pci@1f,2000 at Device 3  Nothing there
Probing /pci@1f,2000 at Device 4  Nothing there
Probing /pci@1f,2000 at Device 5  Nothing there
Probing /pci@6,4000 at Device 0  This slot excluded from probing...
Probing /pci@6,4000 at Device 1  Nothing there
Probing /pci@6,4000 at Device 2  Nothing there
Probing /pci@6,4000 at Device 3  scsi disk tape scsi disk tape
Probing /pci@6,4000 at Device 4  Nothing there
Probing /pci@6,4000 at Device 5  Nothing there
Probing /pci@6,2000 at Device 0  This slot excluded from probing...
Probing /pci@6,2000 at Device 1  network
Probing /pci@6,2000 at Device 2  Nothing there
Probing /pci@6,2000 at Device 3  Nothing there
Probing /pci@6,2000 at Device 4  Nothing there
Probing /pci@6,2000 at Device 5  Nothing there
Probing /pci@4,4000 at Device 0  This slot excluded from probing...
Probing /pci@4,4000 at Device 1  Nothing there
Probing /pci@4,4000 at Device 2  Nothing there
Probing /pci@4,4000 at Device 3  Nothing there
Probing /pci@4,4000 at Device 4  TSI,gfxp
Probing /pci@4,4000 at Device 5  Nothing there
Probing /pci@4,2000 at Device 0  This slot excluded from probing...
Probing /pci@4,2000 at Device 1  Nothing there
Probing /pci@4,2000 at Device 2  Nothing there
Probing /pci@4,2000 at Device 3  Nothing there
Probing /pci@4,2000 at Device 4  Nothing there
Probing /pci@4,2000 at Device 5  Nothing there
Can't open input device.
Keyboard not present.  Using ttya for input and output.
Memory in 2 - way interleave configuration
...Bank #0 256 + 256 + 256 + 256 : 1024 MB
...Bank #1 256 + 256 + 256 + 256 : 1024 MB [Available 2048MB @ 0 ]
...Bank #2 0 + 0 + 0 + 0 : 0 MB [Not In Use]
...Bank #3 0 + 0 + 0 + 0 : 0 MB [Not In Use]
Programming memory controller for 10ns/100MHz UPA timing
Environmental monitor: enabled
Probing Floppy: drive detected on ID0
Probing Audio: audio codec not present
Primary UPA probing
Probing all UPA slots ................................Done.
At UPA Slot  1 Created Node(s)...SUNW,UltraSPARC-II
At UPA Slot  3 Created Node(s)...SUNW,UltraSPARC-II
At UPA Slot  4 Created Node(s)...pci pci
At UPA Slot  6 Created Node(s)...pci pci
At UPA Slot 1f Created Node(s)...pci pci

Sun Enterprise 450 (2 X UltraSPARC-II 480MHz), No Keyboard
OpenBoot 3.22, 2048 MB memory installed, Serial #50976289.
Ethernet address 0:3:ba:9:d6:21, Host ID: 8309d621.

Initializing 1 megs of memory at addr 7fe00000
Initializing 2046 megs of memory at addr 0

分享到QQ

分享到微博

如果你对这篇内容有疑问，欢迎到本站社区发帖提问参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。

发布评论

需要登录才能够评论，你可以免费注册一个本站的账号。

三生路 2022-09-09 02:37:20

我买了一条内存，结果和那3条放到一起使用还是死机，单独测试这些内存没有问题（把原来这组内存与另外1gb那组排除法，）郁闷啊，难道我要订4条吗，烦啊。。

回复收藏 0

极度宠爱 2022-09-08 16:40:44

内存问题

回复收藏 0

陌路终见情 2022-09-08 14:46:11

[AFTO] Multiple Softerrors:
254 Intermittent, 2 Persistent, and 0 Sticky Softerrors accumulated from Memory Module 1904
[AFTO] CONSIDER REPLACING THE MEMORY MODULE.

发现日志中有这个报错，应该是1904内存的问题。我准备弄条试试。

回复收藏 0