层次结构中的别名参数

发布于 2025-02-11 18:02:35 字数 1015 浏览 5 评论 0原文

是否可以使此别名语句工作,因为iob是双向的,我们不能使用分配语句。在所有可用的IOB中,只有特定引脚连接到DDR Memory DQ Bus。我们正在做的另一种方式是包括iob.svh在下面的子模块的实例化期间是所需的片段,并实施了

   module top(
      input [63:0] ddr_dq
    );
    localparam NUM_HB = 24;
    
    logic [NUM_HB-1:0][4-1:0][8-1:0] iob;
      alias iob[0][0][0] = ddr_dq[0];
    
     phy u_phy (
      . iob (iob)
     );
    endmodule
    
    module phy (
      inout [NUM_HB-1:0][4-1:0][8-1:0] iob
    );
    endmodule

这是实施的工作,但是要在上面浏览一下PIN的位置别名语句将是

module top(
  input [63:0] ddr_dq
);
localparam NUM_HB = 24;

logic [NUM_HB-1:0][4-1:0][8-1:0] iob;
  //alias iob[0][0][0] = ddr_dq[0];

 phy u_phy (
  `include iob.svh
 );
endmodule

include incovent iob.svh文件的有用内容。

.iob( {
         nc_iob_pin[0]
        ,ddr_dq[0]
        ,ddr_dq[1]
        ,ddr_dq[2]
        ,ddr_dq[3]
        ,ddr_dq[4]
        ,ddr_dq[5]
})

Is there way to make this alias statement work , as iob is bidirectional we cannot use assign statement. out of all the available iob pins only specific pins are connected to ddr memory dq bus. the other way we are doing is include iob.svh during instantiation of child module below is the snippets of required and implemented

   module top(
      input [63:0] ddr_dq
    );
    localparam NUM_HB = 24;
    
    logic [NUM_HB-1:0][4-1:0][8-1:0] iob;
      alias iob[0][0][0] = ddr_dq[0];
    
     phy u_phy (
      . iob (iob)
     );
    endmodule
    
    module phy (
      inout [NUM_HB-1:0][4-1:0][8-1:0] iob
    );
    endmodule

this is the work around implemented, but to get a the location of pin at single glance above alias statement will be useful

module top(
  input [63:0] ddr_dq
);
localparam NUM_HB = 24;

logic [NUM_HB-1:0][4-1:0][8-1:0] iob;
  //alias iob[0][0][0] = ddr_dq[0];

 phy u_phy (
  `include iob.svh
 );
endmodule

Contents of include iob.svh file is captured below

.iob( {
         nc_iob_pin[0]
        ,ddr_dq[0]
        ,ddr_dq[1]
        ,ddr_dq[2]
        ,ddr_dq[3]
        ,ddr_dq[4]
        ,ddr_dq[5]
})

如果你对这篇内容有疑问,欢迎到本站社区发帖提问 参与讨论,获取更多帮助,或者扫码二维码加入 Web 技术交流群。

扫码二维码加入Web技术交流群

发布评论

需要 登录 才能够评论, 你可以免费 注册 一个本站的账号。

评论(1

⊕婉儿 2025-02-18 18:02:35

我不确定您看到哪个问题。别名语句仅与“ Nets”一起使用,因此将 iob 声明为逻辑,含义var logic可以防止其编译。我确实修改了您的代码以使其编译:

parameter NUM_HB = 24;

module top(
      input [63:0] ddr_dq
    );
    
    wire logic [NUM_HB-1:0][4-1:0][8-1:0] iob; // 'logic' is optional here
      alias iob[0][0][0] = ddr_dq[0];
    
     phy u_phy (
      . iob (iob)
     );
endmodule
    
module phy (
      inout [NUM_HB-1:0][4-1:0][8-1:0] iob
    );
endmodule

I am not sure which problem you saw. Alias statements only work with 'nets', so declaring iob as just logic, meaning var logic prevents it from being compiled. I did modify your code to make it compilable:

parameter NUM_HB = 24;

module top(
      input [63:0] ddr_dq
    );
    
    wire logic [NUM_HB-1:0][4-1:0][8-1:0] iob; // 'logic' is optional here
      alias iob[0][0][0] = ddr_dq[0];
    
     phy u_phy (
      . iob (iob)
     );
endmodule
    
module phy (
      inout [NUM_HB-1:0][4-1:0][8-1:0] iob
    );
endmodule
~没有更多了~
我们使用 Cookies 和其他技术来定制您的体验包括您的登录状态等。通过阅读我们的 隐私政策 了解更多相关信息。 单击 接受 或继续使用网站,即表示您同意使用 Cookies 和您的相关数据。
原文