层次结构中的别名参数
是否可以使此别名
语句工作,因为iob
是双向的,我们不能使用分配
语句。在所有可用的IOB
中,只有特定引脚连接到DDR Memory DQ Bus。我们正在做的另一种方式是包括iob.svh
在下面的子模块的实例化期间是所需的片段,并实施了
module top(
input [63:0] ddr_dq
);
localparam NUM_HB = 24;
logic [NUM_HB-1:0][4-1:0][8-1:0] iob;
alias iob[0][0][0] = ddr_dq[0];
phy u_phy (
. iob (iob)
);
endmodule
module phy (
inout [NUM_HB-1:0][4-1:0][8-1:0] iob
);
endmodule
这是实施的工作,但是要在上面浏览一下PIN的位置别名
语句将是
module top(
input [63:0] ddr_dq
);
localparam NUM_HB = 24;
logic [NUM_HB-1:0][4-1:0][8-1:0] iob;
//alias iob[0][0][0] = ddr_dq[0];
phy u_phy (
`include iob.svh
);
endmodule
include incovent iob.svh
文件的有用内容。
.iob( {
nc_iob_pin[0]
,ddr_dq[0]
,ddr_dq[1]
,ddr_dq[2]
,ddr_dq[3]
,ddr_dq[4]
,ddr_dq[5]
})
Is there way to make this alias
statement work , as iob
is bidirectional we cannot use assign
statement. out of all the available iob
pins only specific pins are connected to ddr memory dq bus. the other way we are doing is include iob.svh
during instantiation of child module below is the snippets of required and implemented
module top(
input [63:0] ddr_dq
);
localparam NUM_HB = 24;
logic [NUM_HB-1:0][4-1:0][8-1:0] iob;
alias iob[0][0][0] = ddr_dq[0];
phy u_phy (
. iob (iob)
);
endmodule
module phy (
inout [NUM_HB-1:0][4-1:0][8-1:0] iob
);
endmodule
this is the work around implemented, but to get a the location of pin at single glance above alias
statement will be useful
module top(
input [63:0] ddr_dq
);
localparam NUM_HB = 24;
logic [NUM_HB-1:0][4-1:0][8-1:0] iob;
//alias iob[0][0][0] = ddr_dq[0];
phy u_phy (
`include iob.svh
);
endmodule
Contents of include iob.svh
file is captured below
.iob( {
nc_iob_pin[0]
,ddr_dq[0]
,ddr_dq[1]
,ddr_dq[2]
,ddr_dq[3]
,ddr_dq[4]
,ddr_dq[5]
})
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我不确定您看到哪个问题。别名语句仅与“ Nets”一起使用,因此将 iob 声明为逻辑,含义
var logic
可以防止其编译。我确实修改了您的代码以使其编译:I am not sure which problem you saw. Alias statements only work with 'nets', so declaring iob as just logic, meaning
var logic
prevents it from being compiled. I did modify your code to make it compilable: