两级分类记忆练习
大家早上好！ 我正在努力进行多层次记忆。有人可以帮我解决吗？
考虑一个256MB大小的2级分页内存，该内存已定位到字节上并由1024页组成，可以说：
（a）逻辑内存，逻辑地址和页面的逻辑内存的尺寸是多少？ （b）物理内存，物理地址和帧的尺寸是多少？ （c）考虑一个等于100N的内存访问时间（没有特定的内存时间 考虑由于分页而引起的开销），访问时间等于具有参数的10NS α等于95％，页面故障时间必须是什么才能使绩效下降。 页面故障管理小于10％，命中率为98％？
Good morning everyone!
I'm struggling with an exercise of multilevel memory. Could someone help me in resolving it?
Consider a 2-level paged memory, with a size of 256MB, addressed to the byte and made up of 1024 pages, lets say :
(a) What are the dimensions of the logical memory, of the logical address and of a page?
(b) What are the dimensions of the physical memory, the physical address and a frame?
(c) Considering a memory access time equal to 100ns (specific memory time without
consider the overhead due to paging), an access time to the TLB equal to 10ns with parameter
α equal to 95%, what the page fault time must be in order for the decrease in performance due to the
page fault management is less than 10% with a hit rate of 98%?
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最合理的假设可能是逻辑地址空间的大小为256 MB，并且每个逻辑地址空间都有1024页。这意味着：
逻辑地址中的位数可以从逻辑地址空间大小确定：
对于2个页面表；必须将逻辑地址分为3个部分：索引到第一级页面表格，第二级页面表中的索引以及页面中的偏移量。从页面大小中，我们可以确定：
我们还知道，逻辑地址的大小必须等于其3件的大小的总和，否则：
现在：我们再次开始陷入麻烦。从理论上讲（实际上，对于某些CPU），第一级页表大小可能与第二级页面表大小不同。
让我们做另一个假设。如果第一级页面表与第二级页面表的大小相同，并且两个索引都必须加起来10位，那么假设两个索引都是5位5位并不是不合理的。
如果页表索引为5位，则页面必须具有
2 ** 5 = 32（或1＆lt;＆lt; 5 = 32）条目。我们知道页面表的大小是：
..但是，因为我们不知道页面表的大小或页面表条目的大小；我们没有足够的信息来确定有关页面表的其他任何信息。
请注意，页面表的大小通常与页面大小（将是256 KIB）相同，在这种情况下，我们可以执行“
页面table Entry = page table of Page Table Sige / page table = page表大小 /条目= 256 KIB / 32 = 8192字节< / code>“。然而;通常，页表条目的大小与物理地址的大小有关（例如32位或4个字节，或64位或8个字节）；和8192字节每个页表条目非常难以置信。这意味着一个或多个假设是错误的（例如，Page表大小和页面大小相等的假设）。物理页面大小等于逻辑页面大小（即256 KIB）是“绝大的可能性”。
没有任何信息可以告诉其他任何有关物理内存尺寸的信息。例如，如果我们可以假设物理地址的大小与页面表的大小相同，则可以确定物理地址空间的大小；但是我们对页面表条目的大小一无所知，因此我们甚至无法做出错误的假设。
我无法理解这个问题。通常，页面故障与TLB命中和TLB失误无关，并且发生：
软件崩溃时（例如
sigsegv信号当您使用非启示指针来尝试访问不存在的记忆的指针）OS必须从辅助存储中获取数据（从swap space，来自文件， ）
OS必须复制数据（例如，将页面设置为“复制在写”，可能是由于以前的
fork（ ），并且页面已写入）Possibly the most plausible assumptions are that the size of a logical address space is 256 MB and that there are 1024 logical pages per logical address space. This means:
The number of bits in a logical address can be determined from the logical address space size:
For 2 levels of page tables; a logical address must be split into 3 pieces: an index into the 1st level page table, an index into the 2nd level page table, and an offset within the page. From the page size we can determine:
We also know that the size of a logical address must equal the sum of the sizes of its 3 pieces, or:
Now we start getting into trouble again. In theory (and in practice for some CPUs) it's possible for the 1st level page table size to be different to the 2nd level page table size.
Let's make another assumption. If 1st level page table is the same size as the 2nd level page table, and both indexes must add up to 10 bits, then it's not unreasonable to assume that the both indexes are 5 bits each.
If a page table index is 5 bits, then a page table must have
2**5 = 32(or1 << 5 = 32) entries.We know that the size of a page table is:
..but because we don't know the size of a page table or the size of a page table entry; we don't have enough information to determine anything else about the page table.
Note that often the size of a page table is the same as the page size (which would be 256 KiB), and in that case we could do "
size of page table entry = page table size / entries per page table = 256 KiB / 32 = 8192 bytes". However; typically the size of a page table entry is related to the size of a physical address (e.g. 32 bits or 4 bytes, or 64 bits or 8 bytes); and 8192 bytes per page table entry is extremely implausible. This would imply that one or more assumptions is wrong (e.g. maybe the assumption that page table size and page size are equal).It's "overwhelmingly likely" that the physical page size is equal to the logical page size (which is 256 KiB).
There's isn't any information that can tell use anything else about the dimensions of physical memory. For example, if we could assume that the size of a physical address is the same as the size of a page table we could determine the size of the physical address space; but we don't know anything about the size of a page table entry so we can't even make possibly false assumptions.
I can't make sense of this question. Typically page faults have nothing to do with TLB hits and TLB misses, and occur when:
software crashed (e.g.
SIGSEGVsignal when you use an uninitialized pointer to attempt to access memory that doesn't exist)the OS has to fetch data from secondary storage (from swap space, from a file)
the OS has to copy data (e.g. a page was set to "copy on write", possibly due to a previous
fork(), and the page was written to)