如何将分析_PORT连接到序列
我有一个序列，需要知道何时在DUT中发生某些事情以决定何时在序列中发送下一个项目，并且我正在尝试找到将这些信息获取到序列的最佳方法。我想将一个分析_PORT连接到序列，因为我的TestBench已经有一个带有所需信息的分析_PORT，但是我的理解是，分析_PORTS需要在Connect_phase中连接，但是UVM_Sequence没有Connect_phase。那么，是否有将Analysis_Port连接到UVM序列的地方？还是有其他方法将信息从分析_PORT获取到序列？
我的用例是： 我正在验证写入缓存，并编写一个将某些商店发送到缓存输入的序列。由于DUT的订购要求和此序列的意图，此序列需要等到在发送下一个商店的输出（书面）上看到每个商店，然后再发送下一个。
I have a sequence that needs to know when certain things have happened in the DUT to decide when to send the next item in the sequence, and I'm trying to find the best way to get that information to the sequence. I wanted to connect an analysis_port to the sequence since my testbench already has an analysis_port with the information I need, but my understanding is that analysis_ports need to be connected in the connect_phase, but uvm_sequence doesn't have a connect_phase. So is there anyway to connect an analysis_port to a uvm sequence? Or is there any other way to get the information from an analysis_port to a sequence?
My use case is the following:
I am verifying a write-through cache and writing a sequence that sends some stores to the input of the cache. Due to ordering requirements of the DUT and the intention of this sequence, this sequence needs to wait until each store is seen on the output of the cache (written-through) before sending the next one.
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您的意思是
Analysis_export或Analysis_imp...如何做到这一点：扩展您的
uvm_sequencer，然后添加Analysis_imp那并在那里实现写函数。写入功能需要以某种方式存储收到的信息，例如将其写入队列（这也将是您的扩展Sequencer类的数据成员）。然后，您的序列可以轻松访问该存储，因为它可以轻松地获得使用
p_sepencer或get_seperencer（）的指针。You mean an
analysis_exportoranalysis_imp...How about doing this: extend your
uvm_sequenceRand add theanalysis_impto that and implement awritefunction there. Thewritefunction needs to store the received information somehow, eg by writing it to a queue (which would also be a data member of your extended sequencer class).Your sequence can then access that store easily, because it can get easily get a pointer to the sequencer using
p_sequencerorget_sequencer().