N-TAP FIR过滤器所需的DSP切片数
我想使用7系列DSP48E1切片来确定实现N-TAP Direct Direct Firef Filter所需的DSP切片的总面积。这些延迟被用作触发器。
计算延迟，乘数，加法器和管道的切片数的方程是什么？图像中显示了要考虑的过滤器。
输入单词长度为15位，系数为14位。使用了两个管道延迟。
请协助。谢谢。 “ 11-tap fir滤波器”>
I want to determine the total area in terms of dsp slices required to implement an N-tap Direct Form 1 FIR filter with pipelining using the 7 Series DSP48E1 slice. The delays are implemented as flip flops.
What are the equations for calculating the number of slices for the delays, multipliers, adders and pipelines. The filter to be considered is shown in the image.
The input word length is 15 bits and the coefficients are 14 bits. Two pipeline delays are used.
Please assist. Thank you.
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Xilinx DSP可以接受多达18位的输入（ noreflow noreferrer“> ref ）。给定的
n您的FIR的TAPS数量，一般公式是您需要每个输出，n乘法和n-1总和。为了实现您所需的拓扑结构，您需要：
nflops [14：0]为延迟链。ndspceil（log2（n））加法器（适用于adder树）。但是，建议是使用内置的蓄能器来实现添加。由于它是管道的，因此您将在每个步骤中积累结果，然后将其传递到下一个乘数。您将必须考虑到延迟，但总体想法是：
可以很容易地映射到xilinx dsp oprive，并且不需要外部逻辑。
Xilinx DSPs can accept inputs up to 18 bits (ref). Given
Nthe number of taps for your FIR, the general formula is that you will need, for each output,Nmultiplications andN-1sums.in order to implement the topology you have pictured here you will need:
NFlip Flops [14:0] for the delay chain.NDSPceil(log2(N))ADDERS (for the adder tree).An advice however, is to use the built-in accumulator to implement the additions. Since it is pipelined, you will accumulate the result at each step and pass it to the next multiplier. You will have to take into account the delays, but the general idea is the following:
That can be mapped pretty easily to the Xilinx DSP primitive and does not require external logic.