FCVTZS D0，D0真的是AARCH64 SIMD指令吗？
GCC似乎将fcvtzs d0，d0作为simd指令进行了分类，但是clang没有。谁是对的？
$ cat toto.s
fcvtzs d0,d0
$ aarch64-linux-gnu-gcc-10 -mcpu=cortex-a53+nosimd -c toto.s
toto.s: Assembler messages:
toto.s:1: Error: selected processor does not support `fcvtzs d0,d0'
$ clang -target aarch64-linux-gnu -mcpu=cortex-a53+nosimd -c toto.s
gcc seems to classify fcvtzs d0,d0 as as SIMD instruction, but clang does not. Who is right?
$ cat toto.s
fcvtzs d0,d0
$ aarch64-linux-gnu-gcc-10 -mcpu=cortex-a53+nosimd -c toto.s
toto.s: Assembler messages:
toto.s:1: Error: selected processor does not support `fcvtzs d0,d0'
$ clang -target aarch64-linux-gnu -mcpu=cortex-a53+nosimd -c toto.s
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您可以将指令分类为实践中的FP和高级SIMD，始终可以一起使用。
我会阅读 fcvtzs的武器定义作为支持GCC对fcvtzs（读取和写作d寄存器）的SISD形式的分类为需要
+SIMD的指令。推理将是指令的编码类（标量单位和双重精节）以及共享的伪代码调用checkfpadvsimdenabled64。我说这个问题有点神秘，因为
checkfpadvsimdenabled64的体系结构伪代码的定义看起来像这样！一种技术性；您的错误消息来自汇编器而不是GCC；直到最近也不同意这两个工具。
You’re far in to the arcane classification of instructions as practically speaking FP and Advanced SIMD are always available together.
I would read the Arm definition of FCVTZS as supporting GCC’S classification of the SISD form of FCVTZS (reading and writing D registers) as an instruction that requires
+simd. The reasoning would be the encoding class of the instruction (Scalar single-precision and double-precision) and the shared pseudo-code callingCheckFPAdvSIMDEnabled64.I say the question gets a bit arcane, because the architecture pseudocode definition of
CheckFPAdvSIMDEnabled64looks like this!One technicality; your error message comes from the assembler not GCC; until recently these two tools also disagreed with each other.