通过以下处理器和缓存性能计算平均内存访问时间
考虑以下处理器和高速缓存配置
| 时钟速率 | 500MHz |
|---|---|
| base CPI | 1 |
| L1 CACHE类型 | 单独的指令和数据缓存 |
| L1 CACHE WRET POLICT策略 | 写入cache |
| l1 cache命中时间 | 2NS |
| l1 list ligh | 40ns（时间是从并从中读取并写入主机内存）L1指令 |
| L1指令高速缓存率 | 1％ |
| L1日期缓存率 | 5％ |
| 脏数据缓存块块 | 的40％数据缓存块 |
（a）计算指令缓存的平均内存访问时间（AMAT）。
（b）计算假设加载和存储的数据缓存的平均内存访问时间（AMAT）表示指令的20％。
我的答案
（a）：
根据公式
amat =命中时间+错过*罚款
AMAT = 2NS+0.01*40NS = 2.4NS
（b）：
根据公式
amat =命中时间+错过*罚款
AMAT = 2NS+0.05* 40NS* 0.2 = 2.4NS
上面的答案是我的意见，但我不确定如何使用缓存配置，例如肮脏的数据缓存块和时钟速率。我的答案是正确的还是我错过了什么？感谢您的阅读！
Consider the following processor and cache configurations
| Clock rate | 500MHz |
|---|---|
| Base CPI | 1 |
| L1 cache type | Separate Instruction and Data Cache |
| L1 cache write policy | Write-back |
| L1 cache hit time | 2ns |
| L1 miss penalty | 40ns(time to read from and write to main memory) |
| L1 instruction cache miss rate | 1% |
| L1 date cache miss rate | 5% |
| dirty data cache blocks | 40% of total data cache blocks |
(a) Compute the average memory access time(AMAT) for Instruction cache.
(b) Compute the average memory access time(AMAT) for data cache assuming load and store represent 20% of instructions.
My answer
(a) :
According to the formula
AMAT= hit time+miss rate* miss penalty
AMAT= 2ns+0.01*40ns =2.4ns
(b) :
According to the formula
AMAT= hit time+miss rate* miss penalty
AMAT= 2ns+0.05* 40ns*0.2 =2.4ns
Above answer is my opinion but I am not sure how to use cache configurations such as dirty data cache blocks and Clock rate. Are my answers right or am I missing something? Thanks for reading!
如果你对这篇内容有疑问，欢迎到本站社区发帖提问 参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。
绑定邮箱获取回复消息
由于您还没有绑定你的真实邮箱，如果其他用户或者作者回复了您的评论，将不能在第一时间通知您！
发布评论
评论（1）
该文本中的Code>和中使用
和的使用是尴尬的。＆nbsp;这可能意味着40ns =读取 +写下，因此40ns用于补充肮脏的高速缓存线，但我认为最好将其读成“两者”，因此可以阅读40ns，也可以将40ns读写为书写。我会在那里写或，以避免从“和”之间的混淆，从“又要”或“也是”的意义上，而在加法的意义上。您的（a）看起来正确。
在（b）上：
L1数据缓存遭受5％的失误率，在40％的情况下，失误必须写下和阅读。＆nbsp;因此，在这里，我们需要区分读取操作和写下操作，因为所有错过的读取时间，而40％也会产生写作时间。
我不用于指定数据的平均访问时间（加载商店），其中包括无法访问数据的说明。＆nbsp;但是，如果您想在某个时候组合I＆amp; D-CACHE TIMES可以全面了解AMAT每说明。＆nbsp;因此，沿着这条路线，我们需要将20％的命中率应用于命中，而不仅仅是错过。＆nbsp;我将在没有20％的情况下计算数据缓存性能（即指令是负载或商店：什么是AMAT），然后将20％的限制为平均为20％。
。
我看不到问题（a）或（b）的周期或MHz。
The use of the conjunction
andin that text is awkward. It could mean that 40ns = read + write-back, so 40ns for refilling a dirty cache line, but I think it is better to read that as "both" instead, so 40ns for read and also 40ns for write-back. I would have writtenorthere instead, to avoid the confusion betweenandin the sense of "both", or "as well", vs. in the sense of addition.Your (a) looks right.
On (b):
The L1 data cache suffers a miss rate of 5% and in 40% of those cases, the miss has to write-back as well as read. So, here, we need to distinguish between the read operations and the write-back operations, since all misses incur read time, while 40% will also incur write-back time.
I am not used to specifying an average access time for data (loads & stores), that includes instructions that don't access data. However, that does make sense if at some point you want to combine the i & d-cache times to get an overall view of the AMAT per instruction. So, going along that route, we need to apply the 20% to both hits and misses not just to misses. I would compute the data cache performance without that 20% (i.e. given the instruction is a load or store: what is the AMAT), then factor that 20% in last to average that out over all instructions.
I don't see cycles or MHz involved in either question (a) or (b).