Modelim verilog中的PS和DELTA值是多少？
我是Modelim的新手。我有一个处理器。在此模块中，时钟周期为40 ps，我以20 ps速度模拟该项目。
forever #20 clk=~clk;
我已经在列表中添加了一些变量，以便能够在每个周期中看到它们的值。但是我已经意识到，有一个时钟周期后发生的 ps delta 值。
这是在80 PS之后创建的。
这是在40 ps之后创建的。（一个时钟周期）
请参见 +1 +1 +2 +3 +4 。我认为它们与某些时间价值有关，但无法完全理解。 我知道在每个@nedege（从1到0到0）中加载PC。我的问题是为什么我会看到不同数量的时钟周期时间。（对于0，有5行，对于20行，只有一个，40等）
为什么它们在列表中的出现视图不同？ ，因为从我的角度来看，当时钟从1更改为0到0当前指令时。但是在图像中，您可以看到 in 40ps行 - 当前指令是不同的。 具有 +1 的一个是当前的指令，但具有 +2 的是下一个指令。
这些三角洲值是什么意思？ 据我所知，Modelim（基于延迟的时序控制，基于事件的时序控制，级别感应的时间控制）有3种不同的时序控制。我想我正在使用@posedge和@NedEdge关键字使用基于延迟的计时控制。
I am new to Modelsim. I have a processor. In this module clock cycle is 40 ps and I simulate the project with 20 ps speed.
forever #20 clk=~clk;
I have added some variables to the list to be able to see their values in each cycle. But I've realized that there are ps and delta values that occur after one clock cycle.
This is created after 80 ps.
This is created 40 ps later.(One clock cycle)
See there are +1 +2 +3 +4. I assume they are related to some time value but couldn't understand exactly.
I know that in each @nedege (towards 0,from 1 to 0) pc is loaded. My question is why do I see different number of clock cycle times.(For 0 there are 5 rows, for 20 there is only one,for 40 there 2 and so on)
Why are their occurrances in the list view different? Because from my perspective when clock is changed from 1 to 0 current instruction is loaded. But in the image as you can see -in 40ps rows- current instruction is different. The one with +1 is current instruction but the one with +2 is next instruction.
And what is the meaning of these delta values?
As far as I know, there are 3 different timing control in Modelsim(delay-based timing control,event-based timing control,level-sensetive timing control). I guess I am using delay-based timing control by using @posedge and @nededge keywords.
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在Verilog Simulators中，时间从事件到事件都会演变，因此它们被称为事件驱动器模拟器。
实际执行会通过安排事件进行推进模拟的许多区域发展。
您看到的是在同一周期中从一个三角洲 - 延迟到另一个的演变。
在20PS时，可能正在发生时钟Negege，并且没有进一步安排任何事件。
在40ps时，可能正在发生时钟的姿势。此事件对等待@posedge的所有信号有效，并且必须更新。因此，调度程序将一些事件添加到事件标题，每个信号一个信号，在最短时间前进（+ 1个delta延迟）后，模拟器评估了最高优先级。
Delta-delay是可能的最低时间持续时间。
如果您打印设计中的所有信号，则可以检查每个事件中的哪个信号。
请记住，同一周期内的进化可能不是确定性的。
更多信息可以在此处找到： https://electronics.stackexchange.com/q/q/99223
In Verilog simulators time evolves from event to event, so they are called event-driver simulators.
Actually execution evolves through a number of region where events are scheduled to advance simulation.
What you are seeing is the evolution from one delta-delay to another in the same cycle.
At 20ps, probably it's happening the clock negedge and no events are scheduled further.
At 40ps, probably it's happening the posedge of clock. This event has effect on all signals that are waiting for @posedge and that have to be updated. So the scheduler adds some events to the event-queue, one each signal, and after minimum time advance (+ 1 delta delay), the simulator evaluates the highest priority one.
Delta-delay is the minimum timeunit advance possible.
If you print all signals in your design, you can check which one is updated at each event.
Remember that evolution inside same cycle could be not deterministic.
More info can be found here: https://electronics.stackexchange.com/q/99223