如何创建一个断言，该断言是否连续3个循环超过3个信号是否不高？

发布于 2025-02-03 02:44:56 字数 308 浏览 2 评论 0原文

我正在尝试为我的Systemverilog设计编写一个断言，该断言检查信号是否从未超过3个周期（隐含地必须被删除）。我的信号称为“ req”，我想到这样做这样的事情：

sequence req_three_seq;
   req ##[1:2] (~req);
endsequence

property reg_three_prop;
   @(posedge clk)
   disable iff (reset)
   (req) |-> req_three_seq;
endproperty

我该怎么做才能创建我需要的断言？

原文

I am trying to write an assertion for my SystemVerilog design which checks if a signal is never high for more than 3 cycles (implicitly it must be de-asserted eventually). My signal is called "req" and I thought about doing something like this:

sequence req_three_seq;
   req ##[1:2] (~req);
endsequence

property reg_three_prop;
   @(posedge clk)
   disable iff (reset)
   (req) |-> req_three_seq;
endproperty

What can I do instead to create the assertion I need?

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酸甜透明夹心 2025-02-10 02:44:56

您始终可以添加一个辅助行的辅助块：

reg [3:0] req_three_buf = 0;
always_ff @(posedge clk) begin
    req_three_buf = {req_three_buf[2:0], req};
end

property reg_three_prop;
    req_three_buf != '1;
endproperty

另外，您可以将块和属性包裹在ifdef中，以免将附加的块和信号提出综合。

You could always add a helper block, something along the lines of:

reg [3:0] req_three_buf = 0;
always_ff @(posedge clk) begin
    req_three_buf = {req_three_buf[2:0], req};
end

property reg_three_prop;
    req_three_buf != '1;
endproperty

Also, you could wrap the block and property in an ifdef, so that you do not pull the additional block and signal into synthesis.

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