为什么Vivado HLS将此AP_Memory接口拆分？
因此，我有以下代码：
int post_quantum_kem_encr( unsigned char m[32],
unsigned char pk[800],
unsigned char coin[32],
unsigned char c[736]) {
#pragma HLS INTERFACE ap_memory port = m
#pragma HLS INTERFACE ap_memory port = pk
#pragma HLS INTERFACE ap_memory port = coin
#pragma HLS INTERFACE ap_memory port = c
#pragma HLS INTERFACE ap_none port = return
some_crypto(m, pk, coin, c);
return crypto_kem_enc_def;
}
合成此问题并将其导出，因为IP在以下IP块中导致：
< img src =“ https://i.sstatic.net/dgn4b.png” alt =“在此处输入图像说明”>
我的问题是，为什么c拆分为<代码> C_D0 和C_D1？ （pk和coin。）对于m而言，这似乎是某种优化的情况。但是，我希望它只是直接对我将其连接的内存元素进行直接单字节访问。
So I have the following bit of code:
int post_quantum_kem_encr( unsigned char m[32],
unsigned char pk[800],
unsigned char coin[32],
unsigned char c[736]) {
#pragma HLS INTERFACE ap_memory port = m
#pragma HLS INTERFACE ap_memory port = pk
#pragma HLS INTERFACE ap_memory port = coin
#pragma HLS INTERFACE ap_memory port = c
#pragma HLS INTERFACE ap_none port = return
some_crypto(m, pk, coin, c);
return crypto_kem_enc_def;
}
Synthesizing this and exporting it as IP results in the following IP block:
My question is, why is c split up into c_d0 and c_d1? (Same goes for pk and coin.) It doesn't happen for m so it seems to be some kind of optimization. I however would like it just to do straight single byte access to the memory element I'm hooking it up to.
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似乎Vivado HLS试图将端口C视为与2端口内存的接口。您可以尝试将以下指令添加到强制1端口模式：
#pragma HLS资源变量= C core = ram_1p
此解决方案看起来像是使用FPGA内部RAM的请求，但似乎它只是配置AP_Memory接口。
ps我在这里找到了一些有关此信息的信息（他们使用core = ram_2p_bram强制2端口接口）： https://www.xilinx.com/content/content/dam/xilinx/support/documents/sw_manuals/xilinx2014_3/ug871-vivado-high-level-level-level--level-synthesis-tutororior..pdf; pages 78-82
It seems that Vivado HLS trying to treat port c as interface to 2-port memory. You can try to add the following directive to force 1-port mode:
#pragma HLS RESOURCE variable=c core=RAM_1P
This solution may look like request to use internal RAM of FPGA, but it seems that it just configures ap_memory interface.
P.S. I found some information about this here (they used core=RAM_2P_BRAM to force 2-port interface): https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2014_3/ug871-vivado-high-level-synthesis-tutorial.pdf; pages 78-82