以下MIPS指令子集的完整MIPS处理器（DataPath＆＃x2B;控制单元）：

发布于 2025-02-02 06:23:34 字数 251 浏览 1 评论 0原文

Alu指令（R-Type）：添加，sub和os，xor，slt 立即说明（i-type）：addi，slti，andi，ori，xori 负载和存储（I-type）：LW，SW 分支（i-type）：beq，bne 跳（J-Type）：J 设计中使用的所有组件的内部电路（Alu，Adder，Extender和...）应包含在您的设计中。您可以使用32位加法器，解码器，多路复用器，内存和寄存器作为设计中的预定义组件，

我找不到任何图像如何组合所有三种类型并进行单个周期过程

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伪装你 2025-02-09 06:23:34

search DataPath图可以找到许多具有用于R型硬件的图像，以及包括分支和负载在内的I-Types。

通常，这些图中缺少的是J型指令，包括J和JAL - 都需要将PC的上部4位与26位相结合立即（有些有此），jal还需要将（下一个）PC捕获到$ ra寄存器中，该寄存器（如果有的话，很少，如果有的话），有这个）。＆nbsp; （JALR通常也缺少，它也需要将返回地址也捕获到一个寄存器中，并设置PC =对方的值的值）。

结合可能显示为无关电路的方法是：剪接。＆nbsp;如果我们执行软件，将两个设计拼接在一起将看起来像：

设计1：

// sequential execution, increment the PC by 1 instruction word
// this is used by R-Types and also I-Types that are arithmetic 
// (and also by I-Types that are conditional branches that are not taken)
PC = PC + 4

设计2：

// branch taken, change flow of control
// this is used by I-Type conditional branches for taken branches, e.g. beq, bne
PC = PC + sxt(imm)`

将这些设计拼接在一起：这需要控制信号才能选择要采用哪种设计，并且鉴于控制信号，组合的设计将能够进行设计1或设计2.＆nbsp;让我们调用控制信号分支。

组合设计1＆amp; 2：

// Choose Design 1 or Design 2 by control of "Branch"
PC = Branch ? PC + sxt(imm) : PC + 4

我们可以在MIPS单周期数据图图中看到，正在完成此剪接 - 控制信号分支告知此PC分配电路是选择顺序执行还是有条件处理的分支地址。＆nbsp; （条件分支电路还检查是否应采用分支，作为控制信号的输出Zero从Alu输出，因此更为复杂，就像pc =（分支＆amp;零）PC + SXT（IMM）：PC +

4当然，这是否需要指标在两个选项之间进行选择（如opeact？option1：option2）

以将三个或多个选项的选择，两个或多个剪接在一起？：可以合并操作员，给定适当的控制信号。

在硬件中，相当于c的？：操作员是mux。＆nbsp; MUX采用三个输入，两个是数据路径输入，一个是（一位，Boolean）控制信号。＆nbsp;然后，MUX根据控制信号的值选择两个输入之一，以传递到其输出。＆nbsp;这与？：运算符：两个DataPath sized（例如32位）输入，一个布尔值输入和一个输出，一个

观察以下MIPS单周期数据图数据图的功能相同，让我们观察到显示的每个Mux都在做这类此类MUX两种不同的设计选择的拼接，以传递什么价值。＆nbsp;每个MUX都有一个控制信号，该信号告诉它要通过的输入，从而忽略了哪个输入。

Search for MIPS single cycle datapath diagram to find many images that have the hardware for R-Types, and I-types including branch and load.

Usually, what's missing from these diagrams is the J-Type instructions, including both j and jal — both need to combine the upper 4 bits of the PC with a 26-bit immediate (some have this), and the jal also needs to capture the (next) PC into the $ra register, which is in the register file (few, if any, have this). (jalr usually also missing, it needs to capture the return address also into one register, and, set the PC = the other register's value).

The approach to combining what might appear as unrelated circuits is: splicing. If we were doing software, splicing two designs together would look like this:

Design 1:

// sequential execution, increment the PC by 1 instruction word
// this is used by R-Types and also I-Types that are arithmetic 
// (and also by I-Types that are conditional branches that are not taken)
PC = PC + 4

Design 2:

// branch taken, change flow of control
// this is used by I-Type conditional branches for taken branches, e.g. beq, bne
PC = PC + sxt(imm)`

Splice these together: this requires a control signal to choose which design to take, and given the control signal, the combined design will be able to do either Design 1 or Design 2. Let's call the control signal Branch.

Combined Designs 1 & 2:

// Choose Design 1 or Design 2 by control of "Branch"
PC = Branch ? PC + sxt(imm) : PC + 4

We can see in the MIPS single cycle datapath diagrams, that this splicing is being done — control signal Branch informs this PC assignment circuitry whether to choose sequential execution or conditional taken branch address. (The conditional branch circuitry also checks to see if the branch should be taken or not, as output by control signal Zero from the ALU, so is a bit more complex, as in PC = (Branch & Zero) ? PC + sxt(imm) : PC + 4)

The main operator for this kind of splicing in C is the ?: pair, the conditional choice, and key here, of course, is the requirement for an indicator to choose between the two options (as in choice ? option1 : option2)

To splice together choice of three or more options, two or more ?: operators can be combined, given appropriate control signals.

In hardware the equivalent of C's ?: operator is the MUX. A MUX takes three inputs, two are data path inputs and one is a (one-bit, i.e. boolean) control signal. The MUX then chooses, based on the value of the control signal one of the two inputs to pass to its output. This is the same functionality as the ?: operator: two datapath-sized (e.g. 32 bit) inputs, one boolean input and one output

Looking at one of these MIPS single cycle datapath diagrams, let's observe that every MUX shown is doing this kind of splicing of two different design choices for what value to pass on. Each MUX is given a control signal that tells it which input to pass through and thus also which one to ignore.

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