如果我有具有以下特征的CPU/系统...
- 16位体系结构（16位寄存器和总线）
- 8总寄存器
- 一组64个汇编指令
，并假设我的汇编指令遵循该格式...
OPCode (6 bits) + Register (3 bits) + Register (3 bits) + Unused (4 bits)
** Example Instructions (below) **
Assembly: LOAD R1, R7 (Loads value of address stored in R1 into destination register R7)
Machine: 110000 001 111 0000
Assembly: STORE R1, R7 (Stores value in R1 into destination address stored in register R7)
Machine: 110001 001 111 0000
这些类型的说明很有意义对我来说，因为所有必需的位都非常适合16位格式，因此可以融入指令登记册（容纳16位），但是我对如何将所需地址进入寄存器感到困惑此指令长度约束？
如果此系统上的地址为16位，在我看来，我需要超过16位来表示将地址值分配给任何给定寄存器在 之前，我什至可以使用诸如负载或商店说明之类的东西……
OPCode (6bits) + destinationRegister (3 bits) + addressLiteral (16 bits) ???
但是，这样的东西不适合我的16位指令寄存器。我在这里不了解什么？非常感谢任何帮助，谢谢！
If I have a CPU/system with the following characteristics...
- 16 bit architecture (16 bit registers and bus)
- 8 total registers
- A set of 64 assembly instructions
And assuming my assembly instructions follow the format...
OPCode (6 bits) + Register (3 bits) + Register (3 bits) + Unused (4 bits)
** Example Instructions (below) **
Assembly: LOAD R1, R7 (Loads value of address stored in R1 into destination register R7)
Machine: 110000 001 111 0000
Assembly: STORE R1, R7 (Stores value in R1 into destination address stored in register R7)
Machine: 110001 001 111 0000
These types of instructions make sense to me because all of the required bits fit nicely into a 16 bit format and thus into the instruction register (which hold 16 bits), but I am confused on how one gets the desired address into a register to begin with due to this instruction length constraint?
If an address is 16 bits on this system, it seems to me like I would need more than 16 bits to represent an instruction that would assign an address value to any given register before I could even use something like a LOAD or STORE instruction...
OPCode (6bits) + destinationRegister (3 bits) + addressLiteral (16 bits) ???
However, something like this would not fit in my 16 bit instruction register. What am I not understanding here? Any help is greatly appreciated, thanks!
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固定长度指令集：
LC-3是一台8寄存器，已固定尺寸的16位说明：它允许在某些16位指令中偏移9位。＆nbsp; 9位偏移量被用作立即形成PC相关地址的立即，从该地址中加载了整个16位值作为数据。＆nbsp;因此，诀窍是将完整的16位值作为数据，在使用它的代码附近的某个地方（例如，+/- 256个单词）。
MIPS是一个32位的指令，在32位地址空间中。＆nbsp;使用两个指令每个具有16位即时值的说明，可以组成完整的32位地址。
hack / nand2tetris具有16位指令，并具有加载常数 /地址的特殊表格，指令表的表格有一个说明它是A型，然后允许15位常数还是地址。 。
Marie是一台累加器机器，具有16位固定长度说明，但只有4K内存，因此允许在16位指令中嵌入12位绝对地址。
PDP-8，一台累加器机器，在12位地址空间中具有12位指令。＆nbsp;说明可以直接引用附近的内存（在与代码相同的128个文字页面中）或零页面上的任何内容（Lowmem，也是128个单词）。
可变长度指令集通常允许按照指令立即立即进行全长，例如x86，68000，其他。处理器将自动包含在说明的全长中的此类即时大小。
要进行更多的元数据，指令集具有格式，并且指令集中的格式将有所不同，以适应不同种类的操作，例如3 reg，vs. 2 reg plus groun-sightimise。＆nbsp;＆nbsp;这一切都用于指令编码，这里的一部分想法是为软件提供所需的功能，同时还可以使硬件实现易于管理。
设计ISA时，需要考虑很多。＆nbsp;一件事是位置独立代码，该代码允许代码在地址空间中的任何地方加载，甚至在不同地址空间中的不同位置共享。理想情况下，代码将在没有任何运行时重新安装的情况下运行，因此代码可以完全不变。＆nbsp;还考虑了动态加载的共享库（DLL）的一些注意事项。
因此，与PC相关的地址模式非常有用，与LC-3，Marie，PDP-8不同，绝对地址应局限于数据，而不允许使用代码。
Fixed-length instruction sets:
LC-3, an 8 register machine, has fixed sized 16-bit instructions: it allows a 9-bit offset in certain 16-bit instructions. The 9-bit offset is used as an immediate to form a pc-relative address, from which a full 16-bit value is loaded as data. So, the trick there is to locate the full 16-bit value as data, somewhere nearby the code that is using it (e.g. within +/-256 words).
MIPS is a 32-bit instruction set, in a 32-bit address space. Using two instructions each having 16-bits of immediate value, a full 32-bit address can be composed.
Hack / nand2tetris has 16-bit instructions and has a special form for loading constants/address, the instruction form has one bit that says whether it is an A-type, which then allows 15 bits of constant or address.
MARIE, an accumulator machine, has 16-bit fixed length instructions, but only 4k of memory, so allows a 12-bit absolute address embedded in the 16-bit instructions.
PDP-8, an accumulator machine, has 12-bit instructions in a 12-bit address space. Instructions can directly reference nearby memory (within the same 128 word page as the code), or any thing on the zero page (lowmem, also 128 words).
Variable length instruction sets often allow a full length immediate following the instruction, such are x86, 68000, others. The processors will automatically include the size of such an immediate in the full length of the instruction.
To go more meta, instruction sets have formats, and the formats within an instruction set will vary to accommodate different kinds of operations, say, 3 reg, vs. 2 reg plus large-ish immediate. It all goes to instruction encoding, and part of the idea here is to offer software the features it needs, while also keeping the hardware implementation manageable.
When designing an ISA, there's a fair amount to think about. One thing is position independent code, which allows code to be loaded anywhere in the address space, and even shared at different locations in different address spaces; ideally code will run without any runtime relocations so the code can be fully immutable. There are also some considerations for dynamically loadable shared libraries (DLLs).
Thus, pc-relative addressing modes are very useful, and, absolute addresses should be confined to data and not allowed in code, unlike LC-3, MARIE, PDP-8.
这是正确的，在带有固定宽度指令的类似RISC的机器中，与地址和寄存器相同的单词大小，将采用多个指令来在寄存器中生成任意常数。
您可以在具有ISA的ISA上进行
ldr r0，= 0x1234567之类的内容时，汇编器可以自动生成附近的“文字池”的ARM，auipcadrp（通过页面）/添加缩放偏移量，add （使用页面内的偏移量进行修复，或将低12位用作<<代码> ldr 指令）lui/addi用于任意非地址常数，有两个直接的宽度，它们加起来为单词大小（例如MIPS 16 + 16，或lui+从普通i-type指令中 +低12的RISC-V高20）您通常需要一个opcode用于指令格式的一个opcode，以获取1个寄存器，然后将其余的用作用作立即钻头，为您提供最大空间。
在您的情况下，6个OpCode位 + 1个寄存器将占9位，只剩下7位。
因此，这还不够，即使在一个寄存器底部添加或ORS的第二个操作码，也不足以在2个说明中生成16位常数。除非您想牺牲多个opcodes（例如，将OpCode的低夫妇用作额外的立即位），那不是很好。
因此，您可能需要使用PC相关负载作为生成大型常数的主要方法。 （因此，一个opcode，1个寄存器，留下7位的偏移，也许按2缩放为2）。
或将整个下一个指令单词读为即时的特殊说明。解码可以考虑此指令，例如跳过数据以及该数据的负载。 （在一个简单的标量管道设计中，也许将其从获取阶段拉出并在其余的管道上发送nop。它需要一堆特殊情况，如果您的管道的危险检测仍在查看，也许会有性能坑洼在用NOP替换并在路径指令中放置一个额外的Muxer或Gate。一些具有16位压缩说明的32位ISA（例如ARM拇指模式或RV32C）具有可变的宽度指令，为2或4个字节，在第一个2字节块中的某些易于定位位张信号。
That's correct, in a RISC-like machine with fixed-width instructions the same word size as addresses and registers, it will take multiple instructions to generate an arbitrary constant in a register.
You can do
ldr r0, =0x1234567)auipcadrp(go by pages) /add(fix it up with the offset within page, or use the low 12 bits as an offset within anldrinstruction)lui/addifor arbitrary non-address constants, with two immediates of widths that add up to the word size (like MIPS 16+16, or RISC-V high 20 fromlui+ low 12 from a normal I-type instruction)You typically want one opcode for an instruction format that takes 1 register, and uses the rest as immediate bits, giving you the max space.
In your case, 6 opcode bits + 1 register would take 9 bits, leaving only 7 immediate bits.
So that's not very much, not enough to even generate a 16-bit constant in 2 instructions even with a 2nd opcode that ADDs or ORs into the bottom of one register. Unless you want to sacrifice multiple opcodes (e.g. use the low couple bits of an opcode as extra immediate bits), that's not very good.
So you might want to use PC-relative loads as the primary way to generate large constants. (So one opcode, 1 register, leaving 7 bits of offset, maybe scaled by 2 so it's word-aligned).
Or a special instruction that reads the whole next instruction word as an immediate. Decoding could consider this instruction like a jump over the data as well as a load of that data. (In a simple scalar pipelined design, maybe pulling it out of the fetch stage and sending a NOP down the rest of the pipe. It would need a bunch of special cases, and maybe have performance potholes if your pipeline's hazard detection still looks at it before replacing with NOP. And puts an extra muxer or AND gate in the path instruction bits take in the decode stage.) I don't know if any real ISAs actually do this; some 32-bit ISAs with 16-bit compressed instructions (like ARM Thumb mode or RV32c) have variable-width instructions that are either 2 or 4 bytes, signalled by some easy-to-decode bits in the first 2-byte chunk.
我假设这是一个虚构的指令集架构，因为基于问题并不是真实的。
样式说明从程序中加载
地址通常使用“立即” 32位值为带有两个32位指令的寄存器。
I am assuming this is a fictional instruction set architecture since based of the question it doesn't seem real.
Addresses are commonly loaded from the program using "immediate" style instructions and therefore would require an instruction outside of the form of "op + reg1 + reg2 + padding"
For example, in MIPS you can use Load Upper Immediate and Load Immediate to load a 32 bit value into a register with two 32 bit instructions.