在VHDL中定义和初始化矩阵的最佳方法

发布于 2025-01-28 23:05:18 字数 618 浏览 3 评论 0原文

我正在尝试制作一个使用VHDL中整数的矩阵（2D数组）的程序，而我以前从未这样做过。

首先，是否可以在实体的信号定义中定义一个2D数组？我的意思是这样的。

entity Matrix is 
Port ( CLK : in STD_LOGIC;
       RESET : in STD_LOGIc;
       Output : out array (integer range <> , integer range <> ) of integer);
end Matrix;

还。实际初始化矩阵的最佳方法是什么？我想做这样的事情；

type 2d_array is array(2 downto 0, 2 downto 0) of integer;

constant A2d : 2d_array :=((1,2,3),
                            (1,2,3),
                            (1,2,3));

不过，我不太确定这是否正确。

最后但并非最不重要的一点是，如果我试图将输出矩阵之一降低到1-D阵列中会发生什么？谁应该解决我的第一个问题，还是会创建一个新问题？

原文

I'm trying to make a program that uses matrices( 2d arrays) of integers in vhdl and i have never done that before.

First of all, is it possible to define a 2d array in the entity's signal definitions?What I mean is something like this;

entity Matrix is 
Port ( CLK : in STD_LOGIC;
       RESET : in STD_LOGIc;
       Output : out array (integer range <> , integer range <> ) of integer);
end Matrix;

Also. What is the best way to actually initialize a matrix ? I thought of doing something like this;

type 2d_array is array(2 downto 0, 2 downto 0) of integer;

constant A2d : 2d_array :=((1,2,3),
                            (1,2,3),
                            (1,2,3));

Still, I'm not really sure if that is correct.

Last but not least, what would happen if i tried to rashape one of the output matrices into an 1-D array? Whould that solve my first problem, or would that create a new one ?

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萌无敌 2025-02-04 23:05:18

在VHDL中，必须在使用前声明所有类型。因此，您不能简单地将对象声明为“数组”，因为您尚未声明类型。要在实体端口定义中使用类型，您通常需要在软件包中声明类型，并将包装包含在实体中。

package my_types_pkg is
  type my_array_t is array(integer range <>, integer range <>) of integer;
end package;

use work.my_types_pkg;

entity Matrix is 
Port ( CLK : in STD_LOGIC;
       RESET : in STD_LOGIc;
       output : out my_array_t -- note this is not yet constrained - the object mapped to this port will constrain the port
     );

初始化：您为2D数组做了正确的事情。

“重塑”：VHDL是一种强烈打字的语言。因此，数组不一定直接转换。整数的2D数组与整数数组的类型不同，因此需要一个类型的转换功能。

In VHDL, all types must be declared before use. So you cannot simply declare an object as an "array" because you have not declared the type yet. To use a type in an entity port definition, you would usually need to declare the type in a package, and include the package in the entity.

package my_types_pkg is
  type my_array_t is array(integer range <>, integer range <>) of integer;
end package;

use work.my_types_pkg;

entity Matrix is 
Port ( CLK : in STD_LOGIC;
       RESET : in STD_LOGIc;
       output : out my_array_t -- note this is not yet constrained - the object mapped to this port will constrain the port
     );

Initialisation : You did the correct thing for a 2d array.

"Reshaping" : VHDL is a strongly typed language. So arrays are not necessarily directly convertible. A 2D array of integers is not the same type as a 1D array of integers, and hence a type conversion function will be required.

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