为什么A和B寄存器在多环形数据PATAPATH中使用？
为什么需要寄存器A和B的寄存器A和B，并且需要readData1和readData2的regressFile需要？难道是否可以直接使用readData1和readData2输出的值？
指令寄存器已经加载了指令，因此IR的值已固定，这意味着在单个指令中，$ rs，$ rt，$ rd reg Nubm显然是相同的。因此，readRegister1和ReadRegister2输入的readRegister1上总是相同的值。因此，除非覆盖寄存器中的相应寄存器被覆盖，否则在RD1和RD2输出上的值是相同的。
这意味着A和B寄存器仅对于需要在上一个周期中覆盖的$ rs或$ rd寄存器值的说明才是必需的。任何人都可以给我一个这样的指示的例子。
Why are registers A and B whose inputs are ReadData1 and ReadData2 of RegisterFile are necessary? Isn't it possible to use directly the values which are on ReadData1 and ReadData2 outputs of Register File?
Instruction Register is already loaded with an instruction, so the value of IR is fixed, which means that $rs, $rt, $rd reg numbers are obviously the same within a single instruction. Hence, there are always the same values on the ReadRegister1 and ReadRegister2 inputs of the Register File. So the values that are on RD1 and RD2 outputs are the same unless the corresponding registers inside RegisterFile are overwritten.
That means that A and B registers are necessary only for the instructions that require to have the values of $rs or $rd registers that were overwritten on previous cycle. Can anybody give me an example of such an instruction.
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一般模式是，在时钟周期中：在时钟开始时，一些寄存器的提要值为计算逻辑，将值馈送到（相同或其他）寄存器到时钟结束时，以便它可以在下一个周期重新开始。
在 单周期数据 中，PC中的值启动了周期的过程，到周期结束时，PC寄存器已更新以重复一个新的周期具有另一个价值。＆nbsp;在此过程中，签发寄存器文件既进行咨询，又（可能）更新。＆nbsp;您可能会注意到这些A＆amp; B寄存器不存在于单个周期数据路径中。
您是正确的，这些值在执行 Multiclecle Datapath上的任何一项指令 上都不会更改。
但是，多环形处理器使用多个周期来执行单个指令（以便可以加快时钟的速度）。＆nbsp;为了支持该处理器设计中的连续周期，使用了一些内部寄存器 - 它们捕获了先前周期的输出，以便下一个周期做一些不同的事情。
多环形数据管图图的问题在于，它们尚不清楚处理器的哪一部分在哪个周期中运行。＆nbsp;那些a＆amp; B寄存器在那里支持一个循环边界，因此解释是在一个周期中发生的，而在另一个周期中进行了算术/alu。＆nbsp; （如果没有这些寄存器，处理器将不得不在随后的周期中再次执行解码，这将降低时钟速率并打败多机关数据的性质。）
在 pipeline dataPath < /strong> 图。＆nbsp;搜索“ MIPS Pipeline Datapath”。＆nbsp; （请注意，某些管道数据图图显示了阶段之间的寄存器，而其他寄存器只需概述什么阶段的内容而不显示这些寄存器。）＆nbsp;大型垂直条是寄存器，它们将管道阶段分开。＆nbsp;当然，管道处理器并行执行所有管道阶段，尽管从理论上讲，相似的边界适用于多环形处理器中的周期。请注意，Pipeline DataPath中的ID/EX管道寄存器可实现A＆amp; B登记在多环形数据管中。
The general pattern is that during a clock cycle: at the start of the clock, some register(s) feed values to computational logic which feed values to (the same or other) register(s) by the end of the clock, so that it can start all over again for the next cycle.
In the single cycle datapath, the value in the PC starts the process of the cycle, and by the end of the cycle, the PC register is updated to repeat a new cycle with another value. Along the way, the register file is both consulted and also (potentially) updated. You may note that these A & B registers are not present in the single cycle datapath.
You are correct that those values do not change during the execution of any one single instruction on the multicycle datapath.
However, the multicycle processor uses multiple cycles to execute a single instruction (so that it can speed the clock). In order to support the successive cycles in that processor design, some internal registers are used — they capture the output of a prior cycle in order for a next cycle to do something different.
The problem with the multicycle datapath diagrams is that they don't make it clear what part of the processor runs in what cycles. Those A & B registers are there to support a cycle boundary, so the decode is happening in one cycle and the arithmetic/ALU in another cycle. (Without those registers, the processor would have to perform decode again in the subsequent cycle, which would decrease the clock rate and defeat the nature of the multicycle datapath.)
Boundaries are made much more clear in pipeline datapath diagrams. Search for "MIPS pipeline datapath". (Note that some pipeline datapath diagrams show registers between stages and others simply outline what's in what stage without showing those registers.) The large vertical bars are registers and they separate the pipeline stages. Of course, the pipeline processor executes all pipeline stages in parallel, though in theory, similar boundaries are applicable to the cycles in a multicycle processor. Note that the ID/EX pipeline register in the pipeline datapath serves the purpose of the A & B registers in the multicycle datapath.