我可以在VHDL中增加一个未签名的号码

发布于 2025-01-28 05:57:40 字数 2472 浏览 3 评论 0原文

因此,我尝试了我在互联网上遇到的主要方法,但它从未起作用,我尝试了许多不同的事情,但似乎无法使其起作用。当应该进行第一次增量时,未签名计数器将从000000升至00000x,然后在第二个增量上将其转到xxxxxxx。

我的代码在下面:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Horloge_3s is
    Port ( rst_n : in STD_LOGIC;
           clk : in STD_LOGIC;
           start_3s : in STD_LOGIC;
           etat_systeme : in STD_LOGIC_VECTOR (1 downto 0);
           end_3s : out STD_LOGIC);
end Horloge_3s;

architecture Behavioral of Horloge_3s is

type states is (notCounting, counting, newGame);
signal current_state, future_state : states;
signal counter, counterInc : unsigned (28 downto 0) := (others => '0');

begin

registre : process(clk, rst_n)
begin
    if rst_n = '0' then
        counter <= "00000000000000000000000000000";
        current_state <= notCounting;
    elsif rising_edge(clk) then
        --if current_state = counting then
            --counter <= counter + 1;
       -- end if; 
        current_state <= future_state;
    end if;
end process;

compteur : process(current_state, counter)
begin
        
    if current_state = counting then
        if counter = "10001111000011010001100000000" then
            end_3s <= '1';
        else
            end_3s <= '0';
            counter <= counterInc + 1;
        end if;
    elsif current_state = notCounting then
        counter <= "00000000000000000000000000000";
        end_3s <= '0';
    elsif current_state = newGame then
        counter <= "00000000000000000000000000000";
        end_3s <= '0';
    end if;

end process;

combiEtats : process(current_state, start_3s, etat_systeme)
begin
    
    if etat_systeme = "00" then
        future_state <= newGame;
    else
        case current_state is
            when notCounting => 
                if start_3s = '1' then
                    future_state <= counting;
                else
                    future_state <= notCounting;
                end if;
            when counting =>
                if counter = "10001111000011010001100000000" then
                    future_state <= notCounting;
                else
                    future_state <= counting;
                end if;
            when newGame => 
                future_state <= notCounting;
            when others => 
                future_state <= notCounting;
        end case;
    end if;
         
end process;      

end Behavioral;

So I tried the main method that I came across on internet and it never worked, I tried many different things but can't seem to make it work. When it is supposed to do the first increment, the unsigned counter will go from 000000 to 00000X and then on the second increment it will go to XXXXXX.

My code just below :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Horloge_3s is
    Port ( rst_n : in STD_LOGIC;
           clk : in STD_LOGIC;
           start_3s : in STD_LOGIC;
           etat_systeme : in STD_LOGIC_VECTOR (1 downto 0);
           end_3s : out STD_LOGIC);
end Horloge_3s;

architecture Behavioral of Horloge_3s is

type states is (notCounting, counting, newGame);
signal current_state, future_state : states;
signal counter, counterInc : unsigned (28 downto 0) := (others => '0');

begin

registre : process(clk, rst_n)
begin
    if rst_n = '0' then
        counter <= "00000000000000000000000000000";
        current_state <= notCounting;
    elsif rising_edge(clk) then
        --if current_state = counting then
            --counter <= counter + 1;
       -- end if; 
        current_state <= future_state;
    end if;
end process;

compteur : process(current_state, counter)
begin
        
    if current_state = counting then
        if counter = "10001111000011010001100000000" then
            end_3s <= '1';
        else
            end_3s <= '0';
            counter <= counterInc + 1;
        end if;
    elsif current_state = notCounting then
        counter <= "00000000000000000000000000000";
        end_3s <= '0';
    elsif current_state = newGame then
        counter <= "00000000000000000000000000000";
        end_3s <= '0';
    end if;

end process;

combiEtats : process(current_state, start_3s, etat_systeme)
begin
    
    if etat_systeme = "00" then
        future_state <= newGame;
    else
        case current_state is
            when notCounting => 
                if start_3s = '1' then
                    future_state <= counting;
                else
                    future_state <= notCounting;
                end if;
            when counting =>
                if counter = "10001111000011010001100000000" then
                    future_state <= notCounting;
                else
                    future_state <= counting;
                end if;
            when newGame => 
                future_state <= notCounting;
            when others => 
                future_state <= notCounting;
        end case;
    end if;
         
end process;      

end Behavioral;

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评论(1

毁梦 2025-02-04 05:57:40

您的计数器在多个过程中分配了,因此它具有多个驱动程序。最初,这起作用,因为它们都在counter上驾驶“ 0”时,您将其初始化为0,但是当您添加一个时,process registre正在从重置和流程中驱动0 compteur现在正在驾驶1,因此您的0和1互相驾驶,导致'x'。解决方案是从一个过程中仅驱动计数器

由于这是一个计数器,因此您确实应该将其从clcok的过程中驱动,而不是组合过程。在组合过程中进行计数器会导致其在0期内在无限循环中计数。

You have counter assigned in multiple processes, hence it has multiple drivers. Initially this works as they are both driving '0' on counter as you initialised it to 0, but when you add one, process registre is driving 0 from the reset and process compteur is now driving 1, hence you have a 0 and 1 driving against each other causing 'X'. Solution is to only drive counter from a single process.

As this is a counter, you really should be driving it from a clcoked process, not a combinatorial one. Having a counter in a combinatorial process will cause it to count up in an infinite loop in 0 time.

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