如何倒入一个包装的阵列

发布于 2025-01-27 17:04:20 字数 374 浏览 4 评论 0原文

logic [4:0] count_zeros;
logic [2:0] id;
integer i;
logic [7:0] [15:0] vld;

always@*
begin
  count_zeros = 5'b0; 
  for (i=0; i<2; i=i+1)
    count_zeros = count_zeros + ~vld[id][i];
end

对于d8的输入，我将count_zeros作为1e。我的预期输出是2。上面的片段中有什么问题？

〜是一个位否定的，！是逻辑上的否定。我要去哪里？

原文

logic [4:0] count_zeros;
logic [2:0] id;
integer i;
logic [7:0] [15:0] vld;

always@*
begin
  count_zeros = 5'b0; 
  for (i=0; i<2; i=i+1)
    count_zeros = count_zeros + ~vld[id][i];
end

For an input as d8, I get count_zeros as 1e. My expected output is 2. What is wrong in the above snippet?

~ is a bitwise negation and ! is logical negation. Where am I going wrong?

分享到QQ

分享到微博

如果你对这篇内容有疑问，欢迎到本站社区发帖提问参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。

发布评论

需要登录才能够评论，你可以免费注册一个本站的账号。

葬﹪忆之殇 2025-02-03 17:04:20

Verilog扩展单个位值（vld [id] [i]）以匹配其所在的表达式的宽度，这是5位，因为count_zeros信号。在应用位倒置操作员之前，这是完成的。由于vld [0] [0]是1'b0，1'b0被扩展到5'b00000 。然后〜（5'b00000）在5'b11111中结果。

创建一个1位信号，例如temp，然后将其直接设置为倒数的位值。然后在添加表达式中使用它。

logic temp;

always @* begin
    count_zeros = 5'b0;
    for (i=0; i<2; i=i+1) begin
        temp = ~vld[id][i];
        count_zeros = count_zeros + temp;
    end
end

请参阅IEEE STD 1800-2017，第11.6节表达位长度。

Verilog expands the single bit value (vld[id][i]) to match the width of the expression it is in, which is 5 bits because of the count_zeros signal. This is done before the bitwise invert operator is applied. Since vld[0][0] is 1'b0, 1'b0 is expanded to 5'b00000. Then~(5'b00000) results in 5'b11111.

Create a 1-bit signal, such as temp, and directly set it to the inverted bit value. Then use it in the addition expression.

logic temp;

always @* begin
    count_zeros = 5'b0;
    for (i=0; i<2; i=i+1) begin
        temp = ~vld[id][i];
        count_zeros = count_zeros + temp;
    end
end

Refer to IEEE Std 1800-2017, section 11.6 Expression bit lengths.

回复收藏 0 原文

~没有更多了~