我收到有关$ readmemh的警告：文件中的单词太多
这是我定义rom模块的方式，
module rom(
input wire [31:0] inst_addr_i,
output reg [31:0] inst_o
);
reg [31:0] rom_mem[0:100];
always@(*) begin
inst_o = rom_mem[inst_addr_i>>2];
end
endmodule
这是$ redmem in tb.v
initial begin
$readmemh("inst.data",tb.rv_soc_ins.rom_ins.rom_mem);
end
和inst.data文件是这样的，有354行。
00000d13
00000d93
00000093
00000113
00208f33
00000e93
00200193
这是执行vpp脚本时我得到的：
$ vvp a.out
WARNING: tb.v:23: $readmemh(inst.data): Too many words in the file for the requested range [0:100].
VCD info: dumpfile gtk.vcd opened for output.
尽管在rom.v中，我已经将ROM设置得足够大。
Here is how I define the rom module
module rom(
input wire [31:0] inst_addr_i,
output reg [31:0] inst_o
);
reg [31:0] rom_mem[0:100];
always@(*) begin
inst_o = rom_mem[inst_addr_i>>2];
end
endmodule
Here is the $readmem in tb.v
initial begin
$readmemh("inst.data",tb.rv_soc_ins.rom_ins.rom_mem);
end
And the inst.data file is like this, which has 354 rows.
00000d13
00000d93
00000093
00000113
00208f33
00000e93
00200193
This is what I get when executing the vpp script:
$ vvp a.out
WARNING: tb.v:23: $readmemh(inst.data): Too many words in the file for the requested range [0:100].
VCD info: dumpfile gtk.vcd opened for output.
Although in rom.v, I have set the rom large enough.
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以上声明意味着您有一个带有101 32位单词的内存。
[0：100]表示内存中有101个位置（地址）。[31：0]表示内存位置（数据）宽32位。您的
inst.data文件中有354行（或行）。您显示的每一行都有一个32位数据字。假设您在文件的其余部分上有一个单词，则文件中有354个单词。警告消息告诉您，您的
rom是 不足以适合文件中的所有数据单词。我在数据文件中添加了一些注释，以说明Verilog对数据的作用：
如您所见，只有前101个数据单词加载到内存中。其余的数据单词不使用。
如果您真的希望您的内存是32x101，并且想摆脱警告，那么您可以从第102行开始删除文件的行，也可以指定开始和结束地址：
如果您真的希望您的内存是32x354，然后您需要更改
rom模块：请参阅IEEE STD 1800-2017，第21.4节，从文件加载内存阵列数据。
The above declaration means that you have a memory with 101 32-bit words.
[0:100]means there are 101 locations (addresses) in the memory.[31:0]means the memory location (data) is 32 bits wide.Your
inst.datafile has 354 rows (or lines) in the file. Each row you showed has one 32-bit data word. Assuming you have one word on each row for the remainder of the file, then you have 354 words in the file.The warning message tells you that your
romis not large enough to fit all the data words in the file.I added some comments to the data file to illustrate what Verilog does with the data:
As you can see, only the first 101 data words are loaded into the memory. The remaining data words are not used.
If you really want your memory to be 32x101 and you want to get rid of the warning, then you can delete the lines of the file starting at line 102, or you could specify start and end addresses:
If you really want your memory to be 32x354, then you need to change the
rommodule:Refer to IEEE Std 1800-2017, section 21.4 Loading memory array data from a file.
警告说您的文件（带有354行）比数组（带有101个元素）更长。
关于VCD的消息没有连接：这只是下一个消息告诉您文件“ gtk.vcd”已打开。
The warning is saying that your file (with 354 rows) is longer than your array (with 101 elements).
The message about VCD is unconnected: it is simply the next message telling you that the file "gtk.vcd" has been opened.