UVM测试结束机制
task mabu_scoreboard::main_phase(uvm_phase phase);
forever begin
# 1ns;
if(extip_rd_req_cnt - extip_rd_rsp_cnt >= `MABU_READ_OST_NUM) begin
hit_rd_max_outstanding = 1;
`uvm_info(get_type_name(),"reach read outstanding threshold!",UVM_NONE);
end else begin
hit_rd_max_outstanding = 0;
end
if(extip_wr_req_cnt - extip_wr_rsp_cnt >= `MABU_WRITE_OST_NUM) begin
hit_wr_max_outstanding = 1;
`uvm_info(get_type_name(),"reach write outstanding threshold!",UVM_NONE);
end else begin
hit_wr_max_outstanding = 0;
end
end endtask
永远循环是在耗时的阶段执行的（main_phase）。由于main_phase不引起异议，该测试可以正确终止。
task mabu_scoreboard::main_phase(uvm_phase phase);
forever begin
# 1ns;
if(extip_rd_req_cnt - extip_rd_rsp_cnt >= `MABU_READ_OST_NUM) begin
hit_rd_max_outstanding = 1;
`uvm_info(get_type_name(),"reach read outstanding threshold!",UVM_NONE);
end else begin
hit_rd_max_outstanding = 0;
end
if(extip_wr_req_cnt - extip_wr_rsp_cnt >= `MABU_WRITE_OST_NUM) begin
hit_wr_max_outstanding = 1;
`uvm_info(get_type_name(),"reach write outstanding threshold!",UVM_NONE);
end else begin
hit_wr_max_outstanding = 0;
end
end endtask
The forever loop is executed in a time-consuming phase (main_phase). The test can get terminated correctly because the main_phase does not raise an objection?
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一个开始耗时的UVM阶段，必须至少提出一个反对意见，以防止该阶段被终止。终止一个阶段意味着所有
uvm_component执行该阶段的过程将被杀死。在您的记分牌示例中，我们必须假设一些其他组件会提出对
main_phase的反对，否则forever循环永远不会完成其第一次迭代。最好使用run_phase进行整个测试需要执行的过程。除了产生时钟外，您的UVM测试台在您的UVM测试台上有任何延迟是不良的做法。 UVM TestBench应该是基于交易的，唯一的延迟应该在于生成时钟。
Forever具有1NS轮询延迟的循环对性能尤其不利。更好的方法是阻止等待活动。One starting a time-consuming UVM phase, there must be at least one objection raised to prevent that phase from being terminated. Terminating a phase means the process of all
uvm_components executing that phase will be killed.In your scoreboard example, we would have to assume some other component raises an objection to the
main_phase, otherwise theforeverloop would never complete its first iteration. It's better to use therun_phasefor a process that needs to execute for the entire test.Having any kind of delay in your UVM testbench except for generation of the clock is a bad practice. A UVM testbench is supposed to be transaction based and the only delays should be in generating your clocks. A
foreverloop with a 1ns polling delay is especially bad for performance. A much better approach is to blocking waiting for an event.是的，这是正确的。由于记分牌中的
main_phase未调用rise_objection，因此计分板不会阻止测试结束。您的大多数测试台组件都不会引起异议。在您的测试中（从
uvm_test延长的类）是在其耗时的阶段提出异议。Yes, that is correct. Since the
main_phasein your scoreboard does not callraise_objection, the scoreboard will not prevent the test from ending.Most of your testbench components will not raise objections. It is common for your test (the class extended from
uvm_test) to raise objections in its time-consuming phase.