[LLVM] [RISCV]将字节载荷/存储促进Word/Dword Loads/Stores的简便方法？
我正在尝试破解Clang/LLVM编译器，以解决我正在处理的处理器上的特定RISC-V硬件问题。
看来，加载地址不是16/32位对齐的地址无法正常工作。为了解决此问题，我想修改编译器以更改所有lb/lbu和sb指令，而是在完整的单词或dword上使用。
例如，我有以下结构：
union Flags
{
struct
{
uint32_t enabled : 1;
uint32_t reserved : 7;
uint32_t foo : 1;
uint32_t reserved2 : 23;
};
uint32_t u32All;
};
现在，当编译程序试图访问包含flags-＆gt; foo的指针时，它可以使用lbu指令来进行位于地址x+1（字节）。此偏移由硬件截断，因此它读取地址x，它将返回enabled flag，而不是foo flag。 我需要将负载促进单词/dword，然后正确操作。
我丝毫不知道LLVM。我已经尝试围绕riscvisellowering.cpp戳戳，但是我唯一要做的就是导致lld在尝试使负载操作合法化时崩溃。
寻找您可能能够提供的任何帮助或指导。谢谢你！
I'm trying to hack the Clang/LLVM compiler to do work around a specific RISC-V hardware issue on the processor I am working on.
It appears that loading addresses that are not 16/32-bit aligned does not work as expected. To work around this, I'd like to modify the compiler to change all lb/lbu and sb instructions to instead work on a full word or dword.
For example, I have the following struct:
union Flags
{
struct
{
uint32_t enabled : 1;
uint32_t reserved : 7;
uint32_t foo : 1;
uint32_t reserved2 : 23;
};
uint32_t u32All;
};
Right now, when the compiled program tries to access a pointer containing Flags->foo, it does so with an lbu instruction that is at address X+1(byte). This offset is truncated by the hardware and so it reads the address X instead, which would return the enabled flag instead of the foo flag.
I need to promote the load into a word/dword and then operate on it properly.
I'm not knowledgeable about LLVM in the slightest. I've tried poking around RISCVISelLowering.cpp, but the only thing I've managed to do is cause lld to crash when it attempts to legalize the load ops.
Looking for any help or guidance you might be able to provide. Thank you!
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