了解Verilog中有限状态机器
我正在使用Artix 7 FPGA，并在Xilinx ISE中编写代码。
我已经有了我正在从事的项目的Verilog代码。不幸的是，我无法理解此模块 - 完整的代码已在此处发布。
我的目标是找出FSM中的这6个状态的定义：重置（000），等待密码（010），比较（100）< /strong>，登录成功（110），登录失败（111）和 do操作（101），然后将编码更改为4位。
我不明白代码中图像中的FSM如何。
有人慷慨地提供帮助吗？我可以说明这里正在做什么吗？
I am using an Artix 7 FPGA and writing my code in Xilinx ISE.
I already have the Verilog code for the project I am working on. Unfortunately, I am not able to understand this module- The full code is posted here.
My goal is to find out where these 6 states are defined in the FSM: Reset (000), Wait for password (010), Compare (100), Log in successful (110), Login failed (111), and Do operation (101) and change the encoding to 4 bits.
I don't understand how the FSM in the image is there in the code.
Is anyone generous enough to help, please? Can I get a description of what is being done here?
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已发布的代码不是Verilog RTL（寄存器传输级别）源代码。相反，它是综合verilog Netlist。它包含供应商原始图，查找表（LUTS，缓冲区等）。无法理解气泡图与链接到链接的后综合网表之间的相关性，该代码是由FPGA构建工具生成的机器（在这种情况下为ISE）。
要关联气泡图和代码，请找到用于创建NetList的相应Verilog源代码。
您可能可以找到这样的源代码：
如果您在Linux上，则CD到代码所在的附近
这是一个verilog rtl状态计算机的示例：
https://wwww.asic-worlld.com/tidbits/tidbits/tidbits/verilog_fsm.html
状态变量和相关逻辑表示为参数名称（Verilog）或枚举（在SystemVerilog中）。使用文本编辑器可以搜索状态名称。
The posted code is not Verilog RTL (Register Transfer Level) source code. Rather, its a post synthesis Verilog netlist. It contains the vendors primitives, look up tables (LUTS, buffers, etc). There is no way to understand the correlation between the bubble diagram and a post synthesis netlist in code linked to, its machine generated by the FPGA build tool (ISE in this case).
To correlate the bubble diagram and code, locate the corresponding Verilog source code that was used to create the netlist.
You might be able to locate the source code like this:
If you are on Linux, cd to near where the code is located and run
Here is an example of what a Verilog RTL state machine would look like:
https://www.asic-world.com/tidbits/verilog_fsm.html
The state variables and related logic are represented as parameter names (Verilog) or enumerations (in SystemVerilog). The state names are searchable using a text editor.