如何控制Vivado的设计中启用？

发布于 2025-01-25 19:09:20 字数 413 浏览 3 评论 0原文

我在vivado中有两个IP如您在图像中所见。

如果我是从随机器发送256位作为消息位作为256位作为CRC输出作为消息位的输出，则在256个消息位传递后出现，我的， 32个CRC位即将出来。当我的这些32 CRC位出来时，我希望我的随机器输入数据停止流动，直到32 CRC位通过。

如何控制这些消息位，或者应该在哪里连接CRC IP的启用。任何建议都得到高度赞赏。

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爱你不解释 2025-02-01 19:09:20

您将需要编写仲裁状态计算机来控制两个块并处理哪个块在什么时间运行的测序。块应使用“启用”或“启动”输入信号以及“完成”或“完成”输出信号，该信号可提供与状态机的握手。

此 page 有很好的解释对状态机器（aka fionally stonity inka fionally stornity inka natione sateed sornity inka natione sornity stornity inka inate in aka in kaa in aka in kaa），他们的意图和用例。

一个示例状态将与以下情况相似，并且需要在一个时钟的过程中进行：

case(arbiter_fsm)
  IDLE : begin
    // Don't do anything when there is no incoming data.
    randomizer_enable <= 1'b0;
    crc32_enable <= 1'b0;
    // If data is coming in, start randomizing.
    if(incoming_data == 1'b1) begin
      randomizer_enable <= 1'b1;
      arbiter_fsm <= RANDOMIZER;
    end
  end
  RANDOMIZER : begin
    randomizer_enable <= 1'b1;
    // Randomize until the data is finished coming in.
    if(randomizer_done == 1'b1) begin
      arbiter_fsm <= CRC32;
      randomizer_enable <= 1'b0;
    end
  end
  CRC32 : begin
    crc32_enable <= 1'b1;
    // Calculate the CRC until it is finished.
    if(crc32_done == 1'b1) begin
      arbiter_fsm <= IDLE;
      crc32_enable <= 1'b0;
    end
  end
  default : begin
    randomizer_enable <= 1'b0;
    crc32_enable <= 1'b0;
    arbiter_fsm <= IDLE;
  end
endcase

You will need to write an arbitration state machine to control the two blocks and handles the sequencing of which block runs at what time. The blocks should be written with an "enable" or "start" input signal and a "finished" or "done" output signal which provides the handshaking with the state machine.

This page has good explanations of how state machines (aka Finite State Machines) are normally constructed, their intent, and use cases.

An example state would be similar to the following and it would need to be in a clocked process:

case(arbiter_fsm)
  IDLE : begin
    // Don't do anything when there is no incoming data.
    randomizer_enable <= 1'b0;
    crc32_enable <= 1'b0;
    // If data is coming in, start randomizing.
    if(incoming_data == 1'b1) begin
      randomizer_enable <= 1'b1;
      arbiter_fsm <= RANDOMIZER;
    end
  end
  RANDOMIZER : begin
    randomizer_enable <= 1'b1;
    // Randomize until the data is finished coming in.
    if(randomizer_done == 1'b1) begin
      arbiter_fsm <= CRC32;
      randomizer_enable <= 1'b0;
    end
  end
  CRC32 : begin
    crc32_enable <= 1'b1;
    // Calculate the CRC until it is finished.
    if(crc32_done == 1'b1) begin
      arbiter_fsm <= IDLE;
      crc32_enable <= 1'b0;
    end
  end
  default : begin
    randomizer_enable <= 1'b0;
    crc32_enable <= 1'b0;
    arbiter_fsm <= IDLE;
  end
endcase

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