您如何下载Nexys视频A7 FPGA的程序？
除了使用Altera培训板在本科生的课程外，我是FPGA世界的新手，但是最近我被分配了与Xilinx Nexys Video A7 FPGA进行一些工作。由于该项目涉及更新固件，因此我的第一个任务是下载当前在FPGA上的现有程序。但是，我找不到在线描述如何做到的任何东西。
一个人甚至可以从FPGA中提取行为中的VHDL程序，还是只能采取一种方式？我发现很难概念化将硬件转回HDL，除非上传后HDL本身存储在板上的某个地方。
同样，我是FPGA世界的新手，很抱歉这是一个愚蠢的问题。感谢您的帮助。
I am new to the world of FPGAs besides a course in undergrad using an Altera training board, but I've recently been assigned to do some work with a Xilinx Nexys Video A7 FPGA. Since this project involves updating firmware, my first task is to download the existing program that is currently on the FPGA. However, I can't find anything online that describes how to do so.
Can one even extract the behavior from an FPGA into a VHDL program, or does it only go one way? I find it hard to conceptualize turning hardware back into HDL unless the HDL itself gets stored somewhere on the board upon upload.
Again, I'm quite new to the FPGA world, so sorry if this is a dumb question. Thank you for your help.
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从Bitstream（用于配置FPGA的二进制文件）对HDL进行反向工程是一项非常困难的任务，甚至可能是不可能的任务。
您可能会提取网列（在单元格级别的电路示意图），这实质上将为您提供如何在FPGA上连接所有逻辑元素。从那里您需要重建实际的硬件，这非常困难（请参阅该步骤及其对硬件逆向工程的复杂性。
在您的情况下，如果您当前的Bitstream是在公司内部生成的，则如果不再可用，则至少应该有一些文档。
如果是购买的设计，我将尝试从那里获得原始设计和工作。
否则，您将不幸，需要重新创建新设计。
Reverse engineering the HDL from the bitstream (what the binary file that is used to configure the FPGA is called) is an extremely difficult task, possibly even an impossible one.
You could possibly extract a netlist (the circuit schematic at the cell level), which would essentially give you how all the logic elements are connected on the FPGA. From there you would need to rebuild the actual hardware, which is extremely difficult (see this paper, which goes into the required steps and their complexity for hardware reverse engineering).
In your case, if your current bitstream was generated inside the company, there should be at least some documentation if the source is no longer available.
If it is a design that was purchased, I would try to get the original design and work from there.
Otherwise, you are out of luck and will need to re-create a new design.