``sigsegv`在Alder Lake效率核心上阅读hw_cpu_cycles

发布于 2025-01-24 19:03:46 字数 1985 浏览 3 评论 0 原文

我想阅读 perf_type_hardware + perf_count_hw_cpu_cycles in intel 12gen上。 这是我的测试程序(基于 cpucycles/amd64rdpmc.c 来自):

#include <linux/perf_event.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/mman.h>
#include <sys/syscall.h>
#include <sys/types.h>
#include <unistd.h>

static struct perf_event_attr attr;
static int fdperf = -1;
static struct perf_event_mmap_page *buf = 0;

long long cpucycles_amd64rdpmc(void) {
  long long result;
  unsigned int seq;
  long long index;
  long long offset;

  if (fdperf == -1) {
    attr.type = PERF_TYPE_HARDWARE;
    attr.config = PERF_COUNT_HW_CPU_CYCLES;
    attr.exclude_kernel = 1;
    fdperf = syscall(__NR_perf_event_open, &attr, 0, -1, -1, 0);
    buf = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ, MAP_SHARED, fdperf, 0);
  }

  do {
    seq = buf->lock;
    asm volatile("" ::: "memory");
    index = buf->index;
    offset = buf->offset;
    asm volatile("rdpmc;shlq $32,%%rdx;orq %%rdx,%%rax"
                 : "=a"(result)
                 : "c"(index - 1)
                 : "%rdx");
    asm volatile("" ::: "memory");
  } while (buf->lock != seq);

  result += offset;
  result &= 0xffffffffffff;
  return result;
}

int main() {

  long long c = cpucycles_amd64rdpmc();
  printf("counter: %llx\n", c);
  return 0;
}

如果我只是运行它,它有时 sigsegv s out,有时会打印一些反值。

如果我将其固定到性能核心 taskset -c n./a.out n 1..15 ,它始终打印出计数器,,,, 如果我将其固定在效率核心上,则使用 n 16..23 它总是 sigsegv s。 因此,我认为这些MSR在这些内核上不可用。

  1. 我在哪里可以找到有关哪些核心的信息的信息?
  2. 效率内核上是否还有另一个PMC( rdtscp )?
  3. 编辑:IT sigsegv rdpmc 带有 rcx = 0x7ffffffff7ea9bd7 的指令

I want to read the PERF_TYPE_HARDWARE + PERF_COUNT_HW_CPU_CYCLES on the Intel 12Gen.
This is my test program (based on cpucycles/amd64rdpmc.c from SUPERCOP) :

#include <linux/perf_event.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/mman.h>
#include <sys/syscall.h>
#include <sys/types.h>
#include <unistd.h>

static struct perf_event_attr attr;
static int fdperf = -1;
static struct perf_event_mmap_page *buf = 0;

long long cpucycles_amd64rdpmc(void) {
  long long result;
  unsigned int seq;
  long long index;
  long long offset;

  if (fdperf == -1) {
    attr.type = PERF_TYPE_HARDWARE;
    attr.config = PERF_COUNT_HW_CPU_CYCLES;
    attr.exclude_kernel = 1;
    fdperf = syscall(__NR_perf_event_open, &attr, 0, -1, -1, 0);
    buf = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ, MAP_SHARED, fdperf, 0);
  }

  do {
    seq = buf->lock;
    asm volatile("" ::: "memory");
    index = buf->index;
    offset = buf->offset;
    asm volatile("rdpmc;shlq $32,%%rdx;orq %%rdx,%%rax"
                 : "=a"(result)
                 : "c"(index - 1)
                 : "%rdx");
    asm volatile("" ::: "memory");
  } while (buf->lock != seq);

  result += offset;
  result &= 0xffffffffffff;
  return result;
}

int main() {

  long long c = cpucycles_amd64rdpmc();
  printf("counter: %llx\n", c);
  return 0;
}

If I just run it, it sometimes SIGSEGVs out, some times it prints some counter value.

If I pin it to performance cores taskset -c N ./a.out with N being 1..15, it always prints the counter,
If I pin it to efficiency cores, with N being 16..23 it always SIGSEGVs.
Hence, I assume that this MSR is not available on those cores.

  1. Where can I find information which MSRs are available on which core?
  2. Is there another PMC for cycles on the efficiency cores (except rdtscp)?
  3. Edit: It SIGSEGV's on the rdpmc instruction with rcx=0x7ffff7ea9bd7

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