如何在测试台上检查状态机案例

发布于 2025-01-24 07:37:30 字数 365 浏览 0 评论 0原文

我正在为SPI奴隶和Wishbone巴士编写代码。问题在于，TestBench文件正确显示了所有信号（在TestBench中使用的信号和端口），但是当我试图在主代码中检查状态计算机时，它没有显示任何红线。我试图定义输出端口并将状态分配给它，它不起作用，因为我不知道如何将输出端口作为字符串制作，因为状态是这样，

TYPE wb_state_t IS
  (
    WB_IDLE,
    WB_WRITE,
    WB_READ,
    WB_FINISH
  );

SIGNAL   wb_state : wb_state_t;

我想分配wb_state到输出端口，以便我可以在测试台中检查状态。我该怎么做？

原文

I am writing a code for spi slave and wishbone bus. The issue is that the testbench file shows all the signals correctly (the signals and ports that are used in testbench) but when I am trying to check the state machine in the main code it shows nothing red line. I tried to define an output port and assign the state to it, it did not work because I don't know how to make an output port as a string because the state is like this

TYPE wb_state_t IS
  (
    WB_IDLE,
    WB_WRITE,
    WB_READ,
    WB_FINISH
  );

SIGNAL   wb_state : wb_state_t;

I want to assign wb_state to an output port so I can check the state in the testbench.
How can I do that?

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追风人 2025-01-31 07:37:30

当您在评论中阅读时，我只需要制作一个简单的软件包，然后将状态机壳放入其中，然后将其称为顶级和TestBench文件。

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
    package wb_state_machine is 
             TYPE wb_state_t IS
      (
        WB_IDLE,
        WB_WRITE,
        WB_READ,
        WB_FINISH
      );
      end package;

As you read in the comments, I only needed to make a simple package and put the state machine cases in it and call it in both the top level and the testbench files.

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
    package wb_state_machine is 
             TYPE wb_state_t IS
      (
        WB_IDLE,
        WB_WRITE,
        WB_READ,
        WB_FINISH
      );
      end package;

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