VHDL如何使用“未签名”信号作为选择确切信号的计数器?
我有执行两个数字乘数的任务,现在我遇到了下一个问题: 在我的代码中,我想将Unsigned I(0至3)用作4位计数器,然后在周期中以某种方式使用i(regb(i))数量的寄存器B,然后将其用于进一步的操作。我试图像以前写的那样(regb(i))做到这一点,但这给了我一个错误。有人可以告诉我,如果有比创建多路复用器更聪明的方法吗?
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity multiplier is
port (A, B : in signed(0 to 10);
rest : in bit;
result : out signed(0 to 10);
ready : out bit := '1';
clk : in bit);
end multiplier;
architecture solution of multiplier is
signal regA, regNB, regRes: signed(0 to 10);
signal regB: signed(0 to 11);
signal i: unsigned(0 to 3) := "0000";
begin
process begin
wait on rest until rest='0' and clk='1';
regA <= A;
regB <= B&'0';
regRes <= (others => '0');
regNB <= -B(0 to 10);
i <= "0000";
ready <= '0';
wait on clk until clk='1';
while i /= "1011" loop
if(regB(i) = '0') then
end if;
wait on clk until clk='1';
i <= i + 1;
end loop;
--wait on clk until clk='1';
ready <= '1';
result <= regA;
end process;
end solution;
I have task to do two number multiplier, and now I am stuck with next problem:
In my code, I had idea to use unsigned i(0 to 3) as 4-bit counter and then in cycle somehow take bit of register B with number of i (regB(i)) and then use it for further actions. I tried to do it simply as I wrote before (regB(i)) but it gives me an error. Could somebody tell me please if there is more clever way to do this than creating a multiplexor?
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity multiplier is
port (A, B : in signed(0 to 10);
rest : in bit;
result : out signed(0 to 10);
ready : out bit := '1';
clk : in bit);
end multiplier;
architecture solution of multiplier is
signal regA, regNB, regRes: signed(0 to 10);
signal regB: signed(0 to 11);
signal i: unsigned(0 to 3) := "0000";
begin
process begin
wait on rest until rest='0' and clk='1';
regA <= A;
regB <= B&'0';
regRes <= (others => '0');
regNB <= -B(0 to 10);
i <= "0000";
ready <= '0';
wait on clk until clk='1';
while i /= "1011" loop
if(regB(i) = '0') then
end if;
wait on clk until clk='1';
i <= i + 1;
end loop;
--wait on clk until clk='1';
ready <= '1';
result <= regA;
end process;
end solution;
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发生错误是因为切片或索引
签名
类型需要使用整数。您已经使用了unsigned
。因此,您需要在索引之前转换类型:旁注:我假设您只想模拟此代码,因为它是不合理的。
You error occurs because slicing or indexing a
signed
type requires the use of integers. You have usedunsigned
. Hence you need to convert the type before indexing:Side note: I assume you only wish to simulate this code as it is not synthesisable.