降低我在Vivado电路的时钟频率
时，我的电路具有这样的
module control(input clk, output out);
reg [63:0] r0 = 1, r1 = 2, r2 = 3, r3 = 4, r4 = 5;
always @ (posedge clk)
begin
// some logic with a high delay -- representative of my actual project
r0 <= (r0 + r1 * r2 % (r3 + 1)) % (r2 + 1) % (r4 + 1) + 2;
r1 <= (r0 + 1) * (r1 + 1) * (r2 + 1) * (r3 + 1) * (r4 + 1) + 2;
r2 <= r0 + r1 + r2 + r3 + r4;
r3 <= r0 + 23;
r4 <= r4 + 1;
end
assign out = |(r0 + r1);
endmodule
当我让Vivado合成并实施此限制
set_property PACKAGE_PIN L1 [get_ports out]
set_property IOSTANDARD LVCMOS33 [get_ports {out}]
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10 -waveform {0 5} [get_ports clk]
限制，我会得到-262.452 ns的最差负懈度，这当然意味着无法满足时序约束。
因此，我的问题的核心是：如何放松定时限制？含义：如何让我的电路以较低的频率运行？
我的情况
- 我的FPGA板有一个100 MHz时钟，我在上面使用的
- 是，我需要在100 MHz附近的任何地方运行电路。即使是100 kHz对我来说也足够快，
- 我认为它可能有可能管道我的逻辑，以便在10 ns的正时限制内运行，但是如果可能的话，我想避免这种情况，因为它会使电路更加复杂
我've尝试过，
- 我已经尝试在每个时钟周期中使用一个寄存器，该寄存器在每个时钟周期中都会增加一个，以便我仅以计数器的一个特定值进行实际逻辑 - 有效地降低了频率。但是，Vivado仍然认为整个逻辑必须在一个时钟周期中完成，因此它报告了与以前相同的负懈度。
- 我已经尝试在约束文件中增加时钟周期 - 这使Vivado认为逻辑可以完成更多的时间，以便似乎可以满足正时约束，但是实际上，当我在实际硬件上测试它时电路仍在原始的100 MHz时钟喂食。
使用较低频率时钟的最简单或最标准的方法是什么？
I have a circuit like this
module control(input clk, output out);
reg [63:0] r0 = 1, r1 = 2, r2 = 3, r3 = 4, r4 = 5;
always @ (posedge clk)
begin
// some logic with a high delay -- representative of my actual project
r0 <= (r0 + r1 * r2 % (r3 + 1)) % (r2 + 1) % (r4 + 1) + 2;
r1 <= (r0 + 1) * (r1 + 1) * (r2 + 1) * (r3 + 1) * (r4 + 1) + 2;
r2 <= r0 + r1 + r2 + r3 + r4;
r3 <= r0 + 23;
r4 <= r4 + 1;
end
assign out = |(r0 + r1);
endmodule
with these constraints
set_property PACKAGE_PIN L1 [get_ports out]
set_property IOSTANDARD LVCMOS33 [get_ports {out}]
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10 -waveform {0 5} [get_ports clk]
When I let Vivado synthesize and implement this, I get Worst Negative Slack of -262.452 ns, which of course means that the timing constraints are not met.
So the core of my question is: How can I relax the timing constraints? Meaning: How can I let my circuit run at a lower frequency?
My Situation
- my FPGA board has a 100 MHz clock which I'm using in the above
- I do not need to run my circuit at anywhere near 100 MHz. Even 100 kHz would be fast enough for me
- I think it could potentially be possible to pipeline my logic so that it runs within the the 10 ns timing constraint, but I want to avoid this if possible because it would make the circuit more complicated
What I've Tried
- I've tried having a register with a counter which I increment by one in every clock cycle and so that I do the actual logic only at one specific value of the counter -- effectively decreasing the frequency. However, Vivado still thinks that the entire logic has to complete in one clock cycle, so it reports the same negative slack as before.
- I've tried increasing the clock period in the constraint file -- that made Vivado think that there is more time for the logic to complete so that the timing constraints could seemingly be met, but actually when I tested it on the real hardware, the circuit was still being fed the original 100 MHz clock.
What is the easiest or most standard way to use a lower frequency clock?
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该电路的多循环路径正时约束是可能的。
然后，整体设计仍将以100 MHz时钟的速度运行，但是特定电路通过组合电路进行了多个循环，同时仍能进行正确的时序分析，以便在您手动给出的周期内关闭时间数量。电路。
然后，您将必须制作一个
start信号，主张一个100 MHz周期，加载新参数，并且完成信号，也要求一个周期，捕获结果。您必须确保在多周期路径中的周期与
start> start和完成脉冲之间的循环之间的匹配。可以在适当的搜索中找到指定多周期定时分析的多周期补丁的详细信息：-)
Multi-cycle path timing constraints for that circuit is a possibility.
The overall design will then still run at 100 MHz clock, but the specific circuit is given multiple cycles for propagation through the combinatorial circuit, while still getting a correct timing analysis that it can close timing within the number of cycles you have manually given for the circuit.
You will then have to make a
startsignal, asserted a single 100 MHz cycle, to load in the new arguments, and adonesignals, also asserted a single cycle, to capture the result.You must ensure a match between the cycles in the multi-cycle path and the cycles in the design between the
startanddonepulses.The details for specifying a multi-cycle patch to Vivado timing analysis can be found in appropriate searches :-)
追踪时钟回到其源以找出它来自何处。许多Xilinx设计将时钟带入零件，并将其运行到MMCM（混合模式时钟管理器）以生成本地时钟。 MMCM可以生成Vivados IP生成工具（IP目录）。它具有用于时钟或生成时钟的参数。更改这些参数以满足您的要求。
它将具有最低频率，您将需要了解其操作才能进行更改。它可以生成的最小时钟频率将取决于其从板输入中的输入时钟。它还具有从板边缘接受的最低频率，根据家庭，部分和速度等级，它将在低MHz范围内。
您可以通过打开Vivado并启动一个新的IP项目，然后选择MMCM来了解它的工作方式，从而学到很多东西。涉及一些相关的Xilinx原语，例如BUFG。它有助于了解BUFG是什么以及如何使用它们。
有关7系列时钟的更多信息：
https://docs.xilinx.com/v/en-en-us/ ug472_7series_clocking
最好为您使用的任何FPGA研究时钟方案，以便您了解时钟的生成位置以及如何生成。
Trace the clock back to its source to find out where it comes from. Many Xilinx designs bring clock into the part and run it to a MMCM (Mixed Mode Clock Manager) to generate the local clock. The MMCM can generated in Vivados IP generation tool (IP Catalog). It has parameters for the clock or clocks it generates. Change those parameters to meet you requirements.
It will have a minimum frequency it can generate, you will need to understand its operation in order to make the change. The minimum clock frequency it can generate will depend on its input clock from the board input. It also has a minimum frequency it can accept from the board edge, that will be in the low MHz range depending on the family, part, and speed grade.
You can learn a lot by opening Vivado and starting a new IP project, then selecting MMCM to see how it works. There are some related Xilinx primitives involved such as bufg's. Its helpful to understand what bufg's are and how they are used.
More info on 7-Series clocking here:
https://docs.xilinx.com/v/u/en-US/ug472_7Series_Clocking
It a good idea to study the clock scheme for any FPGA you work on so that you understand where and how the clock is generated.