计算监管计时器已重置的次数
- 董事会：MSP-EXP432P401R
- MCU：MSP432P401R
我如何计算观察日计时器已重置的次数？ 任何人都可以帮我吗？
- Board: MSP-EXP432P401R
- MCU: MSP432P401R
How do I count the number of times the watchdog timer has been reset?
Can anyone help me in this.
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编写代码以检测是否发生了看门狗重置。微控制器可能具有一个寄存器标志，该寄存器标志指示上一个重置的原因（例如，硬，软，棕色，看门狗等）。在您的MicroController参考手册中的重置或电源控制寄存器中查找此寄存器标志。在系统初始化期间读取此寄存器标志，以检测到观察员重置是否发生。或者，或者，启用看门狗重置中断处理程序可以检测到观察员重置正在发生。
当检测到看门狗重置时，请增加计数器变量并将计数器值保存到非易失性内存中。在系统初始化期间或增加计数之前，从非挥发性内存中读取/还原看门狗计数器值。将计数值保存在非易失性内存中，可以通过功率损失记住计数值。
Write code to detect that a watchdog reset has occurred. The microcontroller may have a register flag that indicates the reason for the previous reset (e.g., hard, soft, brown-out, watchdog, etc.). Look for this register flag in the reset or power control registers in your microcontroller's reference manual. Read this register flag during system initialization to detect that a watchdog reset occurred. Or alternately, enable the watchdog reset interrupt handler to detect that a watchdog reset is occurring.
When a watchdog reset is detected, increment a counter variable and save the counter value to nonvolatile memory. Read/restore the watchdog counter value from nonvolatile memory during system initialization or before incrementing the count. Saving the count value in nonvolatile memory allows the count value to be remembered through a power loss.
ti不容易找到文档！ MSP432FR401数据表的链接断开了参考手册。我只能在各种非TI网站上找到副本。 YMMV。
第3.3.2和3.3.5节分别描述了硬复位状态寄存器。您需要的一个取决于您如何配置看门狗计时器（第4.11.3节）。
重置源是特定于设备的，并且在一般用户手册中未明确说明。它将您转到 datasheet 。不幸的是，据我所知，承诺的信息也不存在！我建议您进行实验，并在重置后读取启动时读取寄存器，并确定哪个位是看门狗重置的唯一位置，而不是说电源重置。 （老实说，我还建议不要使用如此糟糕的文献记录和支持）。
如果您可以确定哪个
rstctl_hardreset_stat/rstctl_softreset_stat_statlit专门与看门狗重置有关，则可以在启动时对其进行测试并增加计数。您的董事会或MCU都没有任何方便的非易失性存储空间。如果您只需要计数看门狗在连续供电的同时重置，则可以将计数器保留在SRAM中的保留位置（一个在启动时不初始化的特定地址，而链接器无法找到数据对象），但是如果您想要一个“终生”计数，然后您可能需要将整个4K Flash扇区专用于柜台（并处理闪光耐力问题 - 如果相关，这可能会值得一个新问题）。TI don't make it easy to find the documentation! The MSP432FR401 datasheet has a broken link to the reference manual. I can only find copies at various non-TI sites such as this. YMMV.
Section 3.3.2 and 3.3.5 describe the hard and soft reset status registers respectively. The one you need depends on how you have configured the watchdog timer (section 4.11.3).
The reset sources are device specific and not explicitly stated in the general user manual. It refers you to the datasheet. Unfortunately as far as I can find, the promised information is not there either! I suggest that you experiment and read the register on start-up following a reset and determine which bit is unique to a watchdog reset rather than say a power-on reset. (To be honest however I'd also suggest not using a part so poorly documented and supported).
If you can determine which
RSTCTL_HARDRESET_STAT/RSTCTL_SOFTRESET_STATbit relates specifically to a watchdog reset, you can test it on start-up and increment your counter. Neither your board or MCU have any convenient non-volatile storage for such a counter. If you only need to count watchdog resets whilst continuously powered, you can keep the counter in a reserved location in SRAM (a specific address not initialised on start-up and not available to the linker to locate data objects), but if you want a "lifetime" count, then you may need to dedicate an entire 4K flash sector to the counter (and deal with the flash endurance issue - that probably warrants a new question if it is relevant).