VHDL中的8位序列到并行变速器

发布于 2025-01-20 18:27:47 字数 990 浏览 0 评论 0原文

我在VHDL中编程了一个8位变速杆:

entity 8b is 
  port(s, clk : in std_logic; p : out std_logic_vector (7 downto 0)); 
end entity; 

architecture arch of 8b is 
  Signal iq : std_logic_vector (7 downto 0); 
begin 
  process(clk) 
  begin 
    if rising_edge(clk) then 
      iq(7) <= s;
      iq(6 downto 0) <= iq(7 downto 1); 
    end if; 
  end process; 
  p <= iq; 
end architecture; 

想法是我要输入并将其提供给我的第一个D-FF。 然后在接下来的7个周期中,其他触发器获得了其他串行输入,这些输入将给予并行输出p。

但是,我不确定此逻辑是否存在缺陷,因为这是我们为此练习提供的解决方案:

architecture behavior of 8b is
  signal p_intern : std_logic_vector(7 downto 0);
begin
  P <= p_intern;
  process(CLK)
  begin
    if rising_edge(CLK) then
      p_intern <= p_intern(6 downto 0) & S;
    end if;
  end process;
end architecture;

但是我没有得到p_intern&lt; = p_inter(6降至0)&amp; S;零件。

有人可以解释一下此背后的逻辑,如果我的版本也有效吗?

I programmed an 8-bit shifter in vhdl:

entity 8b is 
  port(s, clk : in std_logic; p : out std_logic_vector (7 downto 0)); 
end entity; 

architecture arch of 8b is 
  Signal iq : std_logic_vector (7 downto 0); 
begin 
  process(clk) 
  begin 
    if rising_edge(clk) then 
      iq(7) <= s;
      iq(6 downto 0) <= iq(7 downto 1); 
    end if; 
  end process; 
  p <= iq; 
end architecture; 

The idea is that I'm taking input and giving it to my first D-FF.
Then over the next 7 cycles, the other Flip Flops get the other serial inputs which will be given to the parallel output p.

However, I'm not sure if this logic is flawed because this is the solution we got for this exercise:

architecture behavior of 8b is
  signal p_intern : std_logic_vector(7 downto 0);
begin
  P <= p_intern;
  process(CLK)
  begin
    if rising_edge(CLK) then
      p_intern <= p_intern(6 downto 0) & S;
    end if;
  end process;
end architecture;

But I don't get the p_intern <= p_inter(6 downto 0) & S; part.

Can someone please explain the logic behind this and if my version is also valid?

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优雅的叶子 2025-01-27 18:27:47

两种实现之间的唯一区别似乎是行

iq(7) <= s;
iq(6 降到 0) <= iq(7 降到 1); 

p_intern <= p_intern(6 downto 0) & S;

iq 被命名为 p_intern。为了进行比较,我们假设它们都被命名为 iq。

让我们看看他们在做什么:

第一个实现(您的)分配给 iq 的位置:

7     6     5     ... 1     0
s     iq(7) iq(6) ... iq(2) iq(1)

第二个实现(解决方案)分配

7     6     5     ... 1     0
iq(6) iq(5) iq(4) ... iq(0) s

Where iq(6 downto 0) & s 表示“将 s 连接到 iq(6 downto 0) 右侧”。

所以它们并不等价。您的实现会从左侧改变值,而解决方案会从右侧改变值。哪一个是正确的取决于规范(大概解决方案是正确的)。

The only difference between the two implementations seem to be the lines

iq(7) <= s;
iq(6 downto 0) <= iq(7 downto 1); 

vs.

p_intern <= p_intern(6 downto 0) & S;

and that iq is named p_intern. Let's assume they are both named iq for the sake of comparison.

Let's see what they are doing:

The first implementation (yours) assigns to the positions of iq:

7     6     5     ... 1     0
s     iq(7) iq(6) ... iq(2) iq(1)

The second implementation (the solution) assigns

7     6     5     ... 1     0
iq(6) iq(5) iq(4) ... iq(0) s

Where iq(6 downto 0) & s means "concatenate s to the right of iq(6 downto 0)".

So they are not equivalent. Your implementation shifts in the values from the left, and the solution shifts in the values from the right. Which one is correct depends on the specification (presumably the solution is correct).

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