x86地址空间计算PAE到36位
我很难理解 PAE。我知道它通过 PDPT 创建第三级间接，以便地址转换从 CR3 -> CR3 进行。 PDPT(4 条目) -> PD(512 条目) -> PT（512 条目）->页（4096）。但是地址仍然是32位，如何从这个方案中得到36位地址呢？我希望有一个例子。添加另一个表如何“增加”地址空间？
I'm having some hard time understanding PAE. I know it creates a 3rd level of indirection via the PDPT, so that the address translation goes from CR3 -> PDPT(4 entries) -> PD(512 entries) -> PT (512 entries) -> PAGE (4096). But the address is still 32 bits, how do you get 36 bit addresses from this scheme? I'd appreciate an example. How does adding another table "increases" the address space?
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PAE 不会改变 32 位虚拟地址，只会改变它们映射到的物理地址的大小。 （这很糟糕，没有足够的虚拟地址空间来一次映射所有这些物理页面。Linus Torvalds 写了一篇关于 PAE 的精彩咆哮：https://cl4ssic4l.wordpress.com/2011/05/24/linus-torvalds-about-pae/ 最初发布于https://www.realworldtech.com/forum/?threadid=76912&curpostid=76973 / https://www.realworldtech.com/forum/?threadid=76912&curpostid=76980）
它还将 PTE（页表条目）从 4 字节扩大到 8 字节，这意味着 2 个级别已经不够了； 这就是小的额外级别通过这 4 个条目转换虚拟地址的前 2 位的地方。
36 位只是实现 PAE 的第一代 CPU Pentium Pro 中支持的物理地址大小 PAE 没有固有的 36 位限制。
x86-64 采用 PTE 格式，最多可容纳 52 位物理地址。当前的 x86-64 CPU 在带有 PAE 的传统模式下支持与 64 位模式下相同的物理地址大小。 （根据 CPUID 的报告）。该限制是一种设计选择，可以在高速缓存标记、TLB 条目、存储缓冲区条目等以及与它们相关的比较器中保存位。考虑到商业上可用的 DIMM 大小和内存控制器的数量（即使在多插槽系统中），通常选择的 RAM 量要大于实际系统实际可以使用的 RAM 量，并且仍然为某些 I/O 地址空间留出空间。
x86-64 在 PAE 之后不久就出现了，或者说很快就与桌面应用相关了，因此人们普遍误解 PAE 只有 36 位。 （因为 64 位模式是解决更多内存的更好方法，允许单个进程根据用户/内核划分使用超过 2G 或 3G 的内存。）
PAE changes nothing about 32-bit virtual addresses, only the size of physical address they're mapped to. (Which sucks a lot, nowhere near enough virtual address space to map all those physical pages at once. Linus Torvalds wrote a nice rant about PAE: https://cl4ssic4l.wordpress.com/2011/05/24/linus-torvalds-about-pae/ originally posted on https://www.realworldtech.com/forum/?threadid=76912&curpostid=76973 / https://www.realworldtech.com/forum/?threadid=76912&curpostid=76980)
It also widens a PTE (Page Table Entry) from 4 bytes to 8 bytes, which means 2 levels aren't enough anymore; that's where the small extra level comes to translate the top 2 bits of virtual addresses via those 4 entries.
36-bit only happened to be the supported physical address size in the first generation of CPUs that implemented PAE, Pentium Pro There is no inherent 36-bit limit to PAE.
x86-64 adopted the PTE format, which has room for up to 52-bit physical addresses. Current x86-64 CPUs support the same physical address-size in legacy mode with PAE as they do in 64-bit mode. (As reported by CPUID). That limit is a design choice that saves bits in cache tags, TLB entries, store-buffer entries, etc. and in comparators involved with them. It's normally chosen to be more than the amount of RAM that a real system could actually use, given the commercially available DIMM sizes and number of memory controllers even in multi-socket systems, and still leave room for some I/O address space.
x86-64 came soon after PAE, or soon enough for desktop use to be relevant, so it's a common misconception that PAE is only 36 bits. (Because 64-bit mode is a vastly better way to address more memory, allowing a single process to use more than 2G or 3G depending on user/kernel split.)