Modelsim仿真时间周期似乎与test_bench不同

发布于 2025-01-19 02:27:52 字数 1110 浏览 4 评论 0原文

我有一个测试台,该测试台在顶部说明:

'timescale 1 ns/ 1 ps

一个时钟定义为:

testbench中的代码

always begin
   #5 sys_clk = ~sys_clk;
   #20 clk_in = ~clk_in;
   #8 clk_acq = ~clk_asq;
end

使用DO文件运行模拟: vsim in do file

但是,当Cursor测量时,ModelsIm the Clight of Criginem the Cursor测量时,是: 66ns而不是10N 时钟波形 有什么想法吗?

我真的不明白是什么原因导致这种行为。

编辑:另外,如果我在Testbench中运行流浪命令:

initial 
begin
#1 $display("T=0t at time #1",$realtime);
#1 $display("T=0t at time #2",$realtime);
#1 $display("T=0t at time #3",$realtime);
#1 $display("T=0t at time #4",$realtime);
#2 $display("T=0t at time #5",$realtime);
end

我得到:

T=1000 at time #1
T=2000 at time #2
T=3000 at time #3
T=4000 at time #4
T=6000 at time #5

我想这是一个线索,但我不知道是什么原因引起的。

i have a testbench which states at the top:

'timescale 1 ns/ 1 ps

a clock which is defined as:

code in testbench

always begin
   #5 sys_clk = ~sys_clk;
   #20 clk_in = ~clk_in;
   #8 clk_acq = ~clk_asq;
end

run the simulation using a do file:
vsim in do file

but the clock period in ModelSim waveform, when measured by the cursor, is:66ns and not 10ns
clock waveform
any idea?

I don't really understand what causes this behavior.

Edit: also, if i run the fallowing commands in the TESTBENCH:

initial 
begin
#1 $display("T=0t at time #1",$realtime);
#1 $display("T=0t at time #2",$realtime);
#1 $display("T=0t at time #3",$realtime);
#1 $display("T=0t at time #4",$realtime);
#2 $display("T=0t at time #5",$realtime);
end

i get:

T=1000 at time #1
T=2000 at time #2
T=3000 at time #3
T=4000 at time #4
T=6000 at time #5

I guess this is a clue, but i have no idea what causing it.

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马蹄踏│碎落叶 2025-01-26 02:27:52

您应该将所有代码都放在文本形式中。您按照以下方案生成时钟:

always begin
   #5 sys_clk = ~sys_clk;
   #20 clk_in = ~clk_in;
   #8 clk_acq = ~clk_asq;
end

因此,您的时钟每 33 个周期更新一次:5 + 20 + 8,这解释了时钟周期为 66。

always 块不会运行并行作业,也不会重新启动,直到它完成了。因此,它将在再次开始之前完成所有更新。因此,所有时钟的周期都是 66,并且彼此之间会有偏移。

You should have put all the code in text form. You generate clocks following this scheme:

always begin
   #5 sys_clk = ~sys_clk;
   #20 clk_in = ~clk_in;
   #8 clk_acq = ~clk_asq;
end

So, your clocks are updated every 33 cycles: 5 + 20 + 8, which explains clock period of 66.

An always block does not run parallel jobs, nor it restarts till it finishes. So, it will go through all updates before it starts again. As a result all your clocks will have a period of 66 and just will have an offset relative to each other.

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