在 Verilog 中将信号视为时钟
例如，这是我想问的上一个问题的图表。
如果我像这里的图表一样处理数据，并将其写入Verilog代码 这里有什么缺点呢。谢谢回答。
也许我们在使用的工具综合或者实现的时候会遇到一些问题？ 但实际上，当我将上面的代码编程到我的 FPGA 中时，它工作正常。
for example, here is the diagram from previous question in here which I want to ask.
If I treat an data like the diagram here, and write it into Verilog code
What is the disadvantages here. thanks to answer.
Maybe there will be encounter some problems when we are synthesis or implementation in the tools that we use?
but actually it's works okay here when I program the code above into my FPGA.
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简短回答
不可靠的零星行为！
长答案
FPGA与ASIC 设计有时使用所谓的同步设计方法。基本思想是时钟引脚始终由时钟驱动。这使得综合工具能够执行称为“静态时序”的分析，这在一定程度上保证了设计将正常运行，因为所有延迟都已被分析为在设计人员的限制范围内。
在所示设计中，第一级 Q 输出上的延迟将是电路正确运行的决定因素。设计人员希望减少对延迟的依赖，减少对可以通过静态时序分析执行的延迟的担忧。
所示的样式用于较旧的参考文献（我在 90 年代的大学数字设计教科书中有这些），有时是所谓的“波纹计数器”的一部分。在 FPGA 和 ASIC 流行之前，这是一种流行的数字设计方法。当时，数字电路是使用印刷电路板上的离散逻辑来完成的，设计问题是不同的。
找到有关该主题的信息有点困难。这篇文章讨论了一些相同的主题，但没有深入探讨要点。
https:// electronics.stackexchange.com/questions/115967/what-is-a-纹波时钟
很难找到信息的原因之一是“异步设计”一词具有不同的含义，更普遍的含义涉及使用组合逻辑反馈的数字电路设计。逻辑稳定或“锁定”到稳定状态。这与讨论的主要思想是“始终用时钟驱动时钟引脚”不同。
异步设计的另一个不好的做法是使用触发器的异步复位引脚作为控制逻辑。在同步设计中，通常不使用异步复位引脚，当使用它时，其异步置位、同步置低，并且主要用于全局上电复位。
这是对 Xilinx 问题和讨论中讨论的类似问题的答复。
回答论坛。
https://support.xilinx.com/s/question/0D52E0000757EsGSAU/that-dangerous-asynchronous-reset?language=en_US
作者（Xilinx 工程师 Ken Chapman）在答案中使用了“不可靠的零星行为”一词。
另一种（好的）同步设计实践是使用非常低的偏移时钟资源来分配时钟，以便时钟在物理部分的任何地方有效地同时变化。
使用同步设计技术和静态时序作为验证的一部分，并节省更重要问题的调试工作。
自 20 世纪 90 年代以来，“同步设计”一词已被遗忘，并且没有得到广泛使用，它只是设计的完成方式。谷歌搜索“静态计时”将有助于理解这些概念。 “什么是静态时序分析”的完整答案超出了本问题的范围。
执行以下操作作为同步设计的基础：
Short Answer
Unreliable Sporadic Behaviour!
Long Answer
FPGA & ASIC designs use what is sometimes called synchronous design methodology. The basic idea is that clock pins are always driven by a clock. This allows synthesis tools to perform an analysis called 'static timing' which gives a degree of confidence that the design will operate properly because the delays have all been analyzed to be within the designers constraints.
In the design shown, the delay on the Q output of the first stage will be a determining factor on the correct operation of the circuit. Designers want to reduce the dependence on delay reducing the concerns to those that can be performed by static timing analysis.
The style shown is used in older references (my college digital design textbook in the 90's had these) and is sometimes part of what is called a 'ripple counter'. This was a popular method of digital design prior to the prevalence of FPGA and ASIC. In those days digital circuits were done using discrete logic on a printed circuit board, and the design concerns were different.
Its a bit difficult to find information on this topic. This post discussis the same topic a bit but does not go deep on the main point.
https://electronics.stackexchange.com/questions/115967/what-is-a-ripple-clock
One reason that its difficult to find information is that the term 'asynchronous design' has different meanings, and the more ubiquitous meaning pertains to the design of digital circuits where feedback around combinational logic is used. The logic settles or 'latches' into a stable state. This is different than the discussion whose main idea is 'always drive clock pins with a clock'
Another bad practice that was part of asynchronous design was to use the asynchronous reset pin of a flip-flop as control logic. In synchronous design the asynchronous reset pin is often not used, and when it is used, its asserted asynchronously, de-asserted synchronously and used mostly for global power on resets.
This is a reply to a similar issue discussed on the Xilinx question &
answer forum.
https://support.xilinx.com/s/question/0D52E0000757EsGSAU/that-dangerous-asynchronous-reset?language=en_US
The author (Xilinx engineer Ken Chapman) used the phrase 'Unreliable Sporadic Behavior' in the answer.
Another (good) synchronous design practice is to use very low skew clock resources to distribute the clock, so that the clock effectively is changing at the same time everywhere in the physical part.
Use synchronous design techniques & static timing as part of verification and to save debug effort for more important issues.
The term 'synchronous design' has kind of been forgotten since the 90's and is not widely used, its just the way designs are done. Google searching 'static timing' would be helpful to understand these concepts. A complete answer to 'what is static timing analysis' is beyond the scope of this question.
Do the following as a basis for synchronous design: