IO 端口寄存器大小以及设备如何识别地址
我在一篇文章中读到，每个 64k io 端口都分配给 8 位寄存器的地址，当你将 io 端口组合在一起时，你会得到 16 位、32 位等。抱歉，我现在没有在我的历史记录中获取该网站，所以我无法提供链接。 我只是不明白它想说什么，所以我只是把原始表格放在这里
所以我有几点需要确认，因为我很困惑，因为我不小心登陆了另一个网站，他们只是有另一个想法。
i) i/o 端口被分配给外设的寄存器。这些是 16 位的，因为有 64k 端口，并且它们分配到的寄存器可以是任何大小（8、16、32、64 位）。
ii）除了 pci 相关设备外，io 端口地址号是固定的，但在具有配置空间寄存器的设备中，可以使用任何一个想要的数字来分配 io 地址号，只是我不应该被任何其他设备使用。
Que1)当一个地址从处理器出来时，它通过北桥/系统代理到达主板，并根据它拥有的地址映射进行路由，外围设备被告知根据 bar 中配置的内容接受 i/o 范围或内存地址范围，但由于北桥由许多控制器组成[如内存、显卡、pci 等]，但是谁有地址映射来路由。
queii) 根据 intel 82815 gmch 北桥 第 129 页第 4.3 节
“处理器允许在 I/O 内寻址 64K+3 字节 空间。 GMCH 传播处理器 I/O 地址，无需任何 翻译到目的地巴士”
这意味着它只路由 mmio 和 io bar，但如何决定其余的 io 地址（不是由软件或由于 i/o bar 寄存器分配的）。它们应该去哪里以及外围设备如何设备知道它应该接受的这个地址，如果它们只是被扔到总线上，那么特定设备的 CS 引脚是如何决定的
I read in a article about that 64k io port each are address assigned to 8bit register and when you combine io port together you get 16 bit,32bit etc. Sorry i am not getting that website in my history now so i cant provide link.
I just not understood what it want to say so i just put the raw form here
So there are mine few points that i want confirmation on as i am confused bcoz as i accidently land on another website they have just another idea.
i) i/o ports are assigned to registers of peripherals. These are of 16bit as there are 64k port and register they are assigned to can be of any size(8,16,32,64bit).
ii)Except for pci related devices io port address number are fixed,but as in device with configuration space register can be assigned io address number using bar any number one want just i should not be used by anyother device.
Que1)When a address come out of processor it goes to motherboard through northbridge/system_agent and it routes it according to address map it has, peripheral device are told to accept i/o range or memory address range on basis of what was configured in bar,but as northbridge is made up of many controller [like memory,graphics,pci etc] but it is who, who has address mapping to route.
queii) according to intel 82815 gmch northbridge page 129 section 4.3
"The processor allows 64K+3 bytes to be addressed within the I/O
space. The GMCH propagates the processor I/O address without any
translation on to the destination bus"
What does this means it only routes mmio and io bar but than how rest of io address(that are not assigned by software or due to i/o bar register) are decided. where should they go how peripheral device know this address it should acccept,if they are just thrown on the bus than how CS pin is decided of particular device
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