逻辑（二维）信号的算术右移

发布于 2025-01-14 06:14:47 字数 578 浏览 1 评论 0原文

我正在尝试对信号 in 进行右移算术（保留符号）。

当我将值 in[0] 设置为 16'hbb00 时，我预计 in_sign_extend[0] 为 16'hf760< /code> 符号右移后。但是，我注意到在 in_sign_extend[0] 上看到的实际结果是 16'h0680。

localparam CHANNELS = 8;
localparam AXI_M_DATA_WIDTH = 32;

logic signed [0:CHANNELS-1]    [AXI_M_DATA_WIDTH/2-1:0] in;
logic signed [0:CHANNELS-1]    [AXI_M_DATA_WIDTH/2-1:0] in_sign_extend;

assign in_sign_extend[0] = (in[0] >>> 3);

我试图了解 in 是否确实正确签名。或者我在这里遗漏了一些东西。

原文

I am trying to do a Shift Right, Arithmetic (keep sign) on the signal in.

When I set the value in[0] to 16'hbb00, I expect in_sign_extend[0] to be 16'hf760 after it is signed right shifted. But, I notice that the actual result I see on in_sign_extend[0] is 16'h0680.

localparam CHANNELS = 8;
localparam AXI_M_DATA_WIDTH = 32;

logic signed [0:CHANNELS-1]    [AXI_M_DATA_WIDTH/2-1:0] in;
logic signed [0:CHANNELS-1]    [AXI_M_DATA_WIDTH/2-1:0] in_sign_extend;

assign in_sign_extend[0] = (in[0] >>> 3);

I am trying to understand if the in is actually correctly signed. Or am I missing something here.

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相思碎 2025-01-21 06:14:47

打包数组的部分选择始终是无符号的，即使选择整个数组也是如此。只有变量作为整体引用 (in) 才被签名。您可以将代码更改为

assign in_sign_extend[0] = (signed'(in[0]) >>> 3);

或者您可能更喜欢使用未打包的数组

logic signed [AXI_M_DATA_WIDTH/2-1:0] in[CHANNELS];
logic signed [AXI_M_DATA_WIDTH/2-1:0] in_sign_extend[CHANNELS];

assign in_sign_extend[0] = (in[0] >>> 3);

The part select of a packed array is always unsigned, even when selecting the entire array. Only the variable as a whole reference (in) is signed. You can change your code to

assign in_sign_extend[0] = (signed'(in[0]) >>> 3);

Or you might prefer to use an unpacked array

logic signed [AXI_M_DATA_WIDTH/2-1:0] in[CHANNELS];
logic signed [AXI_M_DATA_WIDTH/2-1:0] in_sign_extend[CHANNELS];

assign in_sign_extend[0] = (in[0] >>> 3);

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