STM32F4 定时器触发 DMA SPI –国家安全服务问题
我有一个 STM32F417IG 微控制器和一个外部 16 位 DAC (TI DAC81404)，它应该生成采样率为 32kHz 的信号。通过 SPI 的通信不应占用任何 CPU 资源。这就是为什么我想使用定时器触发的 DMA 将数据以 32kHz 的速率移位到 SPI 数据寄存器，以便将数据发送到 DAC。
有关 DAC 的信息 每当 DAC 接收到通道地址和新的相应 16 位值时，DAC 就会将其输出电压更新为新接收到的值。这是通过以下方式实现的：
- 将 CS/NSS/SYNC – 引脚拉至低电平
- 发送 24 位/3 字节长消息并将
- CS 拉回高电平状态 消息的前 8 位除其他信息外还包含应在何处施加输出电压的信息。下一个和最后一个 16 位同时包含新值。
有关STM32的信息 不幸的是，ST 的微控制器的 NSS 引脚存在硬件问题。通过 SPI 开始通信，NSS 引脚被拉低。现在，只要 SPI 启用，该引脚就处于低电平（。（参考手册第 877 页）。遗憾的是，这不是与需要在每条消息后增加 NSS 的设备进行通信的正确方式。“解决方案”将是按照手册中的建议手动切换 NSS 引脚（当主机与需要在传输之间取消选择的 SPI 从机通信时，NSS 引脚必须配置为 GPIO 或必须使用另一个 GPIO，并且切换的通过软件。）
问题 如果以普通方式使用 DMA，则仅在启动进程时使用 CPU。通过每 1/32000 秒切换 NSS 两次，这会导致相应的 CPU 交互。 我的问题是我是否为了实现没有CPU的通信而错过了一些东西。
如果不是的话，我现在的目标是将 CPU 处理时间减少到最低限度。我的计划是用定时器触发 DMA。因此，每隔 1/32k 秒，SPI 的数据寄存器就会填充 DAC 的 24 位数据。 NSS 可以通过定时器中断来切换。 我在实现它时遇到问题，因为我不知道如何使用 HAL 函数将定时器与 SPI 的 DMA 链接起来。谁能帮助我吗？
I have a STM32F417IG microcontroller an external 16bit-DAC (TI DAC81404) that is supposed to generate a Signal with a sampling rate of 32kHz. The communication via SPI should not involve any CPU resources. That is why I want to use a timer triggered DMA to shift the data with a rate of 32kHz to the SPI data register in order to send the data to the DAC.
Information about the DAC
Whenever the DAC receives a channel address and the new corresponding 16bit value the DAC will renew its output voltage to the new received value. This is achieved by:
- Pulling the CS/NSS/SYNC – pin to low
- Sending the 24bit/3 byte long message and
- Pulling the CS back to a high state
The first 8bit of the message are containing among other information the information where the output voltage should be applied. The next and concurrently the last 16bit are containing the new value.
Information about STM32
Unfortunately the microcontroller of ST are having a hardware problem with the NSS-pin. Starting the communication via SPI the NSS-pin is pulled low. Now the pin is low as long as SPI is enabled (. (reference manual page 877). That is sadly not the right way for communicate with device that are in need of a rise of the NSS after each message. A “solution” would be to toggle the NSS-pin manually as suggested in the manual (When a master is communicating with SPI slaves which need to be de-selected between transmissions, the NSS pin must be configured as GPIO or another GPIO must be used and toggled by software.)
Problem
If DMA is used the ordinary way the CPU is only used when starting the process. By toggling the NSS twice every 1/32000 s this leads to corresponding CPU interactions.
My question is whether I missed something in order to achieve a communication without CPU.
If not my goal is now to reduce the CPU processing time to a minimum. My pIan is to trigger DMA with a timer. So every 1/32k seconds the data register of SPI is filled with the 24bit data for the DAC.
The NSS could be toggled by a timer interrupt.
I have problems achieving it because I do not know how to link the timer with the DMA of the SPI using HAL-functions. Can anyone help me?
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这是一个棘手的问题。对于 DAC 和微控制器的这种组合，可能很难避免每个样本发生一次中断。
然而，我会考虑的一种方法是将 CS 信号创建为定时器输出比较（如 PWM）。您可以使用同一定时器的多个通道或链接多个定时器来在 CS 输出和 DMA 触发之间创建延迟。您应该为抖动留出一些空间，因为根据发生的其他情况，DMA 可能不会立即响应。但这不会损害您的 DAC 输出信号，因为它仅输出片选上升沿上的值（在 DAC 数据表中称为 SYNC），该值仍然来自您的第一个定时器。
This is a tricky one. It might be difficult to avoid having one interrupt per sample with this combination of DAC and microcontroller.
However, one approach I would look at is to have the CS signal created as a timer output-compare (like PWM). You can use multiple channels of the same timer or link multiple timers to create a delay between the CS output and the DMA trigger. You should allow some room for jitter, because depending on what else is happening the DMA might not respond instantly. This won't hurt your DAC output signal though, because it only outputs the value on the rising edge of chip select (called SYNC in the DAC datasheet) which will still be from your first timer.