使用OpenCL FPGA进行压缩设计
我正在研究有损压缩器，我想知道哪种方式更适合设计，第一种是将数据传输到全局内存，直到处理完所有数据，第二种方式是使用管道或通道来传递数据。
I am working on a lossy compressor, and I am wondering which way is more suitable for the design, the first one is to transfer data to the global memory until all the data is processed and the second way is to use either pipes or channels to pass data.
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由于我一直在研究有损压缩算法，所以我可以说显然两者都是有用的。然而，它取决于很多因素。
例如，它取决于您的工作负载大小、取决于底层 FPGA、取决于您特定的有损压缩算法等。
借助 OpenCL 管道和通道，您可以利用英特尔 FPGA 的内部带宽并避免瓶颈使用片外存储器。显然，当数据在生成时被消耗时，您会减少存储需求。但所有这些优势都是以 OpenCL 内核之间额外的握手逻辑为代价的；渠道管道将更加高效
但如果其级通过由同一时钟脉冲驱动的电线或寄存器连接，则在布局和布线时序收敛方面可扩展性较差。
下面更新的答案：
既然您在评论中提到了以下内容：
要处理的数据至少有 500 MB，所以空间很大：
是的，这是一个很大的块。尽管英特尔 Aria 10 没有高带宽内存 (HBM)，但如果可能，请尝试使用其结构上具有高带宽内存 (HBM) 组的 FPGA。 FPGA 器件中的 HBM 有助于克服带宽（内存）瓶颈。
此外，由于在许多应用程序中，主要目标之一是不丢失任何数据，因此您可以考虑利用无损压缩算法。请查看此调查论文，其中他们给出了FPGA 上的压缩算法示例将帮助您了解案例中的设计目标。
另请检查OpenCL 中的 Gzip 压缩 OpenCL 设计示例将指导您。 Gzip 是一种广泛使用的压缩和解压缩方法。此设计示例展示了使用适用于 OpenCL 的英特尔 FPGA SDK 的压缩实现。
如果您想知道 OpenCL 管道和通道将如何帮助您，那么当然 构造并发数据结构
on FPGA with Channels 可以为您提供一些指导。
Since I have worked on lossy compression algorithms, I can say apparently both can be useful. However, it depends on a lot of factors.
For instance, it depends on the size of your workload, it depends on the underlying FPGA, it depends on your particular lossy compression algorithm and etc.
With OpenCL pipes and channels, you can leverage internal bandwidth of the your Intel FPGA and avoid the bottleneck of using off-chip memory. And apparently you reduce your storage requirements when data is consumed as produced. But all these advantages come at the cost of additional handshaking logic between your OpenCL kernels; the channel pipeline will be more efficient
but less scalable in terms of place and route timing closure if its stages are connected by wires or registers pulsed by the same clock.
Below Updated Answer:
Since you mentioned following in your comment:
The data to be processed would be at least 500 MB so huge space:
Yes, that's a big chunk. Although Intel Aria 10 does not have a High-Bandwidth Memory (HBM), if it's possible try a FPGA with High Bandwidth Memory (HBM) banks on it's fabric. HBM in FPGA devices helps overcoming the bandwidth (memory) bottleneck.
Additionally, since in many applications one of the main goals is not to lose any data, therefore you consider leveraging lossless compression algorithms. Please check this survey paper where they give examples of compression algorithms on FPGAs that will help you understand the design goals in your case.
Also please check Gzip Compression OpenCL Design Example in OpenCL that will guide you. Gzip is a widely used compression and decompression method. This design example presents a compression implementation using Intel FPGA SDK for OpenCL.
And if you want to know how OpenCL pipes and channels will help you, then of course Constructing Concurrent Data Structures
on FPGA with Channels can provide you some directions.