如果有8核cpu,理论上OS可以同时写入8个文件?

发布于 2025-01-12 01:03:31 字数 95 浏览 0 评论 0原文

如果有8核cpu,理论上OS可以同时写入8个文件而不需要上下文切换?

顺序写入8个1gb文本文件和同时写入8个1gb文本文件速度有很大差异吗?(使用线程或多进程)

If there are 8 core cpu, theoretically OS can write 8 files at the same time with out context switching?

Is there a big difference in speed between writing 8 1gb text files sequentially and at the same time?(using thread or multiprocess)

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千鲤 2025-01-19 01:03:31

您对磁盘传输有很大的误解。如今,磁盘 IO 不再由 CPU 完成。它曾经用于当 CPU 必须从 IO 端口读取/写入数据时 (https://wiki. osdev.org/ATA_PIO_Mode)。 ATA PIO 模式是最新(且仍受支持)的非 DMA 硬盘传输模式。

否则,您有一个 AHCI,它是一个控制硬盘的 PCI 设备。 AHCI 是与现代 SATA 硬盘交互的规范 (https://www.intel.ca/content/www/ca/en/io/serial-ata/serial-ata-ahci-spec-rev1-3-1.html)。它不控制 NVME 磁盘。 NVME 是一个单独的类,必须由具有不同接口的专用 PCI 控制器控制 (https://wiki。 osdev.org/NVMe)。

如果我没记错的话,PCI 总线是串行的。他们一次传输一位。它们可以非常快,并且 PCI 规范用于高端服务器,PCI-SIG 小组经常发布新规范,旨在提供新功能(新速度、新机制等)。

在 PCI 中,您写入 RAM 中的一些常规位置,这些位置写入设备的 PCI 寄存器。这通常称为内存映射 IO (MMIO)。可以肯定的是,它比你在问题中所说的要复杂得多。 8 核 CPU 不会同时写入 8 个文件。即使在没有 DMA 的系统中,读取的 IO 端口也只能从硬盘上的一个特定位置归档一些数据。不能同时被8个核心读取。

我对 AHCI 不太确定,但通常情况下,PCI 硬件接口几乎不需要锁定。它们在 RAM 中具有必须像操作队列一样进行修改的结构。可以肯定的是,如果一个核心修改了队列,则另一个核心不得也触及队列中的相同位置。如果8个核心必须执行文件IO,则8个核心会将其操作添加到AHCI的DMA作业队列中。我从未实现过 AHCI 驱动程序,但 AHCI 规范(第 5 章)中指出:

AHCI 的数据结构是假设 HBA 中的每个端口都包含自己的 DMA 引擎,即每个端口都可以独立于任何其他端口执行。这是软件的自然流程,因为每个设备通常被视为单独的执行线程。强烈建议 HBA 实施以这种方式进行。

软件向端口的 HBA 提供命令列表,然后由 HBA 处理这些命令。对于命令列表深度为“1”的 HBA,这是单步操作,软件仅呈现单个命令。对于支持命令列表的 HBA,可以发布多个命令。

软件将操作系统收到的新命令发布到列表中的空槽中,并设置 PxCI 寄存器中相应的槽位。 HBA 不断查看 PxCI 以确定是否有命令要传输到设备。

这里,HBA 指的是 AHCI 规范的芯片实现(实际芯片)。我不太确定这意味着什么,但我认为这意味着多个 DMA 作业可以同时发生,但可能不是来自同一设备/硬盘。由于大多数计算机上只有一个主硬盘,因此我猜想同一个磁盘不会同时执行 8 个 DMA 作业,因为“CPU 中有 8 个核心”。

You have big misconceptions about disk transfers. Disk IO isn't done by the CPU nowadays. It used to when the CPU had to read/write the data to/from an IO port (https://wiki.osdev.org/ATA_PIO_Mode). The ATA PIO mode is the latest (and still supported) hard-disk transfer mode that isn't DMA.

Otherwise, you have a AHCI which is a PCI device that will control hard-disks. The AHCI is a specification for interacting with modern SATA hard-disks (https://www.intel.ca/content/www/ca/en/io/serial-ata/serial-ata-ahci-spec-rev1-3-1.html). It doesn't control NVME disks. NVME are a separate class and must be controlled by a specialized PCI controller that has a different interface (https://wiki.osdev.org/NVMe).

If I'm not wrong, PCI buses are serial. They transfer one bit at a time. They can be very fast and the PCI specification is used in high end servers with new specifications announced every so often by the PCI-SIG group that aim at providing new capabilities (new speed, new mechanisms, etc).

In PCI, you write to some conventional positions in RAM which writes to the PCI registers of the device. This is often called Memory Mapped IO (MMIO). It is certain that it is much more complex than what you say in your question. A CPU with 8 cores doesn't write 8 files simultaneously. Even in a system without DMA, the IO port that is read can only be filed with some data from one specific position on the hard-disk. It cannot be read by 8 cores at once.

I'm not so sure for the AHCI but, normally, the PCI hardware interfaces require almost no locking. They have structures in RAM that must be modified like queues of operations. It is certain that if one core modifies the queue another core must not also touch the same position in the queue. If 8 cores must do file IO, the 8 cores will add their operation to the queue of DMA jobs of the AHCI. I never implemented an AHCI driver but it is stated in the AHCI specification (on chapter 5) that:

The data structures of AHCI are built assuming that each port in an HBA contains its own DMA engine, that is, each port can be executed independently of any other port. This is a natural flow for software, since each device is generally treated as a separate execution thread. It is strongly recommended that HBA implementations proceed in this fashion.

Software presents a list of commands to the HBA for a port, which then processes them. For HBAs that have a command list depth of ‘1’, this is a single step operation, and software only presents a single command. For HBAs that support a command list, multiple commands may be posted.

Software posts new commands received by the OS to empty slots in the list, and sets the corresponding slot bit in the PxCI register. The HBA continuously looks at PxCI to determine if there are commands to transmit to the device.

Here, HBA refers to the silicon implementation of the AHCI specification (the actual chip). I'm not exactly sure what this means but I think it means that several DMA jobs can happen at once but probably not from the same device/hard-disk. Since on most computers there is only one main hard-disk then I guess there isn't going to be 8 DMA jobs at once from the same disk because "there is 8 cores in the CPU".

っ左 2025-01-19 01:03:31

无论CPU核心如何,操作系统都可以一次打开多个文件并写入,但瓶颈是硬盘。即使你有 8 核 cpu,你写入的所有数据也必须按顺序写入硬盘。

然而,现代操作系统不会直接写入文件,因此如果您同时打开并写入 8 个文件,它将存储在 RAM 上并放入队列中以写入硬盘驱动器,因此每当硬盘驱动器空闲时,它就会获取该数据从 RAM 并将其写入磁盘。

Os can open many files and write at a time regardless of the cpu cores but the bottleneck is hard-drive. Even if you have 8 core cpu all of your data that you write have to go sequentially to the hard-drive.

However modern OS don't write directly to files so If you open and write 8 files at same time it is going to stored on RAM and puts in queue for writing to hard-drive so whenever hard-drive gets free it will take that data from ram and write it to the disk.

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