不同的结构元素“由连续和过程性赋值写入”。

Question

为什么我得到：

# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[0]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[1]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[2]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[0].subar[3]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[0]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[1]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[2]' written by continuous and procedural assignments. See testbench.sv(19). 
# ** Error (suppressible): testbench.sv(27): (vopt-12003) Variable 'ar[1].subar[3]' written by continuous and procedural assignments. See testbench.sv(19). 

对于这段代码：

module tb;

logic clk;

struct {
  struct {
    logic seq;
    logic assig;
    logic seq2;
  } subar [4];
} ar [2];


always_ff @(posedge clk) begin
  for (int i=0; i<2; i++) begin
    for (int j=0; j<4; j++) begin
      ar[i].subar[j].seq <= '1;
    end
  end
end

generate
  for (genvar i=0; i<2; i++) begin
    for (genvar j=0; j<4; j++) begin
      assign ar[i].subar[j].assig = '1;
    end
  end
endgenerate

always_ff @(posedge clk) begin
  for (int i=0; i<2; i++) begin
    for (int j=0; j<4; j++) begin
      ar[i].subar[j].seq2 <= '1;
    end
  end
end

endmodule

所有三个逻辑在结构内部都是独立的，并且它们没有分配在两个不同的块中。

EDA Playground：https://www.edaplayground.com/x/qYZ9

替换generate/分配与always_comb

always_comb begin
  for (int i=0; i<2; i++) begin
    for (int j=0; j<4; j++) begin
      ar[i].subar[j].assig = ar[i].subar[j].seq;
    end
  end
end

将生成与分配替换为always_comb块给出了不同的结果，因为所有*.seq信号是X。

每个 assig = seq 在每个 i 和 j 迭代之间都是独立的。

为什么这是无效的？

无法使用结构来对信号进行分组实在是太烦人了......

Answer 1

该错误消息是由于 IEEE 1800-2017 SystemVerilog LRM。基本上，由于 i 是一个变量索引，因此 ar[i] 的长静态前缀是 ar 并且任何数组或结构选择后续的无关紧要。工具已经更加乐观地对待这个问题，但这是一个渐进的过程。

您可以全局抑制错误，也可以重写代码，将 for 循环从块移出到生成 for 循环中。

module tb;

logic clk;

struct {
  struct {
    logic seq;
    logic assig;
    logic seq2;
  } subar [4];
} ar [2];

for (genvar  i=0; i<2; i++) begin
  for (genvar  j=0; j<4; j++) begin
always_ff @(posedge clk) begin
      ar[i].subar[j].seq <= '1;
    end
  end
end

  for (genvar i=0; i<2; i++) begin
    for (genvar j=0; j<4; j++) begin
      assign ar[i].subar[j].assig = '1;
    end
  end

for (genvar  i=0; i<2; i++) begin
  for (genvar  j=0; j<4; j++) begin
    always_ff @(posedge clk) begin
      ar[i].subar[j].seq2 <= '1;
    end
  end
end

endmodule