解析错误:意外的 WHEN,期望分号
我正在尝试在 VHDL 中实现此 when else 语句,但由于某种原因,我收到此错误:
Line 48. parse error, unexpected WHEN, expecting SEMICOLON
第 48 行是这个:LED<= "1111001" when count_temp = "0001" else
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SOURCE is
Port (clk_in,RST : in STD_LOGIC;
COUNT : inout STD_LOGIC_VECTOR (3 downto 0);
AN: out std_logic_vector(3 downto 0);
LED: out std_logic_vector(6 downto 0));
end SOURCE;
architecture Behavioral of SOURCE is
signal count_temp: std_logic_vector(3 downto 0);
signal CLK: std_logic;
component clk_div is
port (clk_in: in std_logic;
clk_out: out std_logic);
end component;
begin
CL: clk_div port map (clk_in, CLK);
counter: process (CLK,RST,count_temp)
begin
if (RST = '1')then
count_temp <= "0000";
elsif(rising_edge(CLK))then
if (count_temp <= "1111") then
count_temp <= count_temp +1;
else count_temp <= "0000";
end if;
end if;
end process;
COUNT <= count_temp;
AN <= "1110";
process(count_temp)
begin
LED<= "1111001" when count_temp = "0001" else
"0100100" when count_temp = "0010" else
"1111001" when count_temp = "0011" else
"0100100" when count_temp = "0100" else
"1111001" when count_temp = "0101" else
"0100100" when count_temp = "0110" else
"0100100" when count_temp = "0111" else
"1111001" when count_temp = "1000" else
"0100100" when count_temp = "1001" else
"1111001" when count_temp = "1010" else
"0100100" when count_temp = "1011" else
"1111001" when count_temp = "1100" else
"0100100" when count_temp = "1101" else
"1111001" when count_temp = "1110" else
"0100100" when count_temp = "1111" else
"0100111" when others;
end process;
I am trying to implement this when else statement in VHDL but for some reason, I get this error:
Line 48. parse error, unexpected WHEN, expecting SEMICOLON
Line 48 is this one: LED<= "1111001" when count_temp = "0001" else
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SOURCE is
Port (clk_in,RST : in STD_LOGIC;
COUNT : inout STD_LOGIC_VECTOR (3 downto 0);
AN: out std_logic_vector(3 downto 0);
LED: out std_logic_vector(6 downto 0));
end SOURCE;
architecture Behavioral of SOURCE is
signal count_temp: std_logic_vector(3 downto 0);
signal CLK: std_logic;
component clk_div is
port (clk_in: in std_logic;
clk_out: out std_logic);
end component;
begin
CL: clk_div port map (clk_in, CLK);
counter: process (CLK,RST,count_temp)
begin
if (RST = '1')then
count_temp <= "0000";
elsif(rising_edge(CLK))then
if (count_temp <= "1111") then
count_temp <= count_temp +1;
else count_temp <= "0000";
end if;
end if;
end process;
COUNT <= count_temp;
AN <= "1110";
process(count_temp)
begin
LED<= "1111001" when count_temp = "0001" else
"0100100" when count_temp = "0010" else
"1111001" when count_temp = "0011" else
"0100100" when count_temp = "0100" else
"1111001" when count_temp = "0101" else
"0100100" when count_temp = "0110" else
"0100100" when count_temp = "0111" else
"1111001" when count_temp = "1000" else
"0100100" when count_temp = "1001" else
"1111001" when count_temp = "1010" else
"0100100" when count_temp = "1011" else
"1111001" when count_temp = "1100" else
"0100100" when count_temp = "1101" else
"1111001" when count_temp = "1110" else
"0100100" when count_temp = "1111" else
"0100111" when others;
end process;
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看起来可能有两件事:
2)。根据此页面 https://www.ics.uci.edu/~jmoorkan /vhdlref/cond_s_a.html。您编写 else 部分的方式看起来像是一些语法错误?也许只需要
else "0100111"
(其他时候不需要)It looks like perhaps two things:
2). Per this page https://www.ics.uci.edu/~jmoorkan/vhdlref/cond_s_a.html. It looks like some syntax error for how you wrote the else part? Maybe just need
else "0100111"
(no when others)