TI CC2541 adc 分压器值错误
我正在开发一个使用 TI CC2541 的项目（放置在 jdy-08 BLE 模块上）。我尝试使用 adc 接口获取锂电池电量。我引用了这篇文章 https://sunmaysky.blogspot.com/2013/12/cc2530-adc-howto-in-ti-z-stack.html?m=1 。要读取 adc 值，我使用以下代码：
uint16 adc_ain2=0;
HalAdcSetReference(HAL_ADC_REF_125V);
adc_ain2=HalAdcRead(HAL_ADC_CHN_AIN2,HAL_ADC_RESOLUTION_10);
如果我不使用分压器并直接将电压源连接到 P0_2 引脚，则没有问题。 例如：
0,35V ==> adc 170
0,70V ==> adc 310
1,17V ==> adc 498
但如果我使用分压器，我会得到错误的值（R1 = 820K，R2 = 820K）。 例如：
0,33V ==> adc 347
0,53V ==> adc 368
提前谢谢您！
I am working on a project with TI CC2541 (placed on a jdy-08 BLE module). I try to get a lipo battery level by using adc interface. I refered this post https://sunmaysky.blogspot.com/2013/12/cc2530-adc-howto-in-ti-z-stack.html?m=1 . To read adc value i use this code:
uint16 adc_ain2=0;
HalAdcSetReference(HAL_ADC_REF_125V);
adc_ain2=HalAdcRead(HAL_ADC_CHN_AIN2,HAL_ADC_RESOLUTION_10);
If i dont use voltage divider and directly connect a voltage source to P0_2 pin there is no problem.
eg:
0,35V ==> adc 170
0,70V ==> adc 310
1,17V ==> adc 498
But if i use a voltage divider i get wrong values (R1 = 820K, R2 = 820K).
eg:
0,33V ==> adc 347
0,53V ==> adc 368
Thank you in advance!!
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从 ADC 中获得正确答案：
答案可能是您的外部电阻网络延长了 ADC 的时间常数，导致采样电容器无法在采样窗口内达到输入电压。
我在这里写了一篇更长的文章： “使用 ADC：基础知识，为什么我会得到有趣的读数以及如何解决它？”。如果您还不熟悉该主题，我强烈建议任何使用模拟输入的人阅读它。
这是针对您的具体问题的快速版本，据我快速阅读后了解。
基本概念是所有（或几乎所有）ADC 都有一个开关电容器网络来对输入进行采样。当电容器无法在分配给它的时间内充电并对输入进行采样时，他们会给您错误的答案。
以下是 SPICE 中直接连接到 ADC 输入级的电阻分压器的示例。
在第一幅图中，迹线是 ADC 输入处的电压（红色）和驱动采样网络中两个开关的时钟脉冲（灰色）。该模型来自应用笔记
"LTSpice，模拟 SAR ADC模拟输入”。
您可以看到输入端（也是分压器网络中的抽头）电压有很大的下降，并且在第一个开关 S1 打开以将电容器与输入分离之前它不会恢复。
此时第二开关S2通常将电容器连接到读出电路。在该模型中，它在下一个时钟周期将电容器接地。但想象一下 S2 关闭之前的最终状态保持固定，直到读出完成。
为了完全清楚发生了什么，该图显示了采样电容器上的电压。如上所述，当 S1 打开且转换将在实际 ADC 中开始时，电压尚未达到预期的位置。这可能是你的阅读错误。
最好的解决方案是使用运算放大器和 RC 网络作为 SAR 电容器的电荷库，如下所示：
在下图中，您可以看到为电容器充电的电流来自外部电容器中存储的电荷，并且只有一个小的快速电压尖峰可以为电容器充电。
第二个最佳解决方案是至少使用一个运算放大器缓冲器，如下图所示。在这种情况下，缓冲器提供足够的电流以使采样电容器能够快速恢复。它看起来像一个大的负向电压尖峰，并且运算放大器的输入端也有一个小尖峰。
同样，可能值得看一下文章此处（点击）
Getting the right answer from your ADC:
The answer is probably that your external resistor network is lengthening the time constant for the ADC such that the sampling capacitor fails to reach the voltage of the input within the sampling window.
I have a longer write up about this here: "Using an ADC: Basics, why do I get funny readings and how do I fix it? ". I very much suggest reading it for anyone using an analog input if you are not already knowledgeable in the subject.
Here is a quick version for your specific issue, as I understand it on quick perusal.
The essential concept is that all (or maybe almost all) ADC's have a switched capacitor network to sample the input. They give you the wrong answer when that capacitor is not able to charge up within the time allotted for it too sample the input.
Here is an example in SPICE for a resistor divider connected directly to the input stage of an ADC.
In the first figure the traces are the voltage at input to the ADC (red) and the clock pulse (grey) that drives the two switches in the sampling network. The model comes from an application note
"LTSpice, simulating SAR ADC analog inputs".
You can see there is a large sag in the voltage at the input (also the tap in the divider network) and it does not recover before the first switch S1 opens to detach the capacitor from the input.
The second switch S2 would normally connect the capacitor to the read-out circuit at this point. In the model it grounds the capacitor for the next clock cycle. But just imagine the final state before S2 closes being held fixed until the readout is done.
To be completely clear about what is going on, this figure shows the voltage on the sampling capacitor. As above, the voltage is not yet where it is supposed to be by the time S1 opens and the conversion would begin in an actual ADC. That is probably your erroneous reading.
The best solution is to us an opamp and RC network to act as a charge reservoir for the SAR capacitor, like this:
In this next figure you see that the current flow to charge up the capacitor comes from charge stored in that external capacitor and that there is only a small fast voltage blip to recharge the capacitor.
The second best solution is use at least an opamp buffer, as in the following figure. The buffer in this case provides enough current for the sampling capacitor to be able to recover quickly. It looks like a large negative going voltage spike and there is a small pike on the input to the opamp as well.
Again, it may be worthwhile to take a look at the write-up here (click)