FPGA 时序收敛：如何约束 2 个时钟之间的路径或如何强制保留路径？
在 Lattice Verilog FPGA 设计中，我有两个 PLL 生成的时钟，频率相同，均为 125MHz (8ns)，但第二个时钟与第一个时钟相差 90°：
wire clk;
wire clk90; //clk90 is clk with phase at 90°
pllm pllm_inst(.CLKI(oscInternal), .CLKOP(clk), .CLKOS(clk90));
reg [63:0] wbuf;
always @(posedge clk) begin
wbuf <= wbuf + 1;//Fake logic
end
wire [31:0] sdram_dq_tx;
ODDRXE ODDRXE00_inst(.D0(wbuf[0]), .D1(wbuf[16]), .SCLK(clk90), .RST(1'b0), .Q(sdram_dq_tx[0]));
...
该设计非常拥挤，所有时钟均出现以下 HOLD 错误wbuf：
Error: The following path exceeds requirements by 1.585ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram_inst/wbuf[0] (from clkop +)
Destination: FF Data in sdram_inst/ODDRXE00_inst (to clkop2 +)
Delay: 0.380ns (34.5% logic, 65.5% route), 1 logic levels.
Constraint Details:
0.380ns physical path delay sdram_inst/SLICE_1029 to ddr_Dq[0]_MGIOL exceeds
-0.011ns DO_HLD and
0.000ns delay constraint less
-1.976ns skew less
0.000ns feedback compensation requirement (totaling 1.965ns) by 1.585ns
如何将两个时钟之间的路径限制为彼此 90°，以关闭我的设计时序？强制 wbuf 保持 2ns（8ns 的 90°）是否有意义？如何在时间限制下实现这一目标？
In a Lattice Verilog FPGA design, I have two PLL-generated clocks at the same frequency 125MHz (8ns) but the second clock is at 90° shift of the first clock:
wire clk;
wire clk90; //clk90 is clk with phase at 90°
pllm pllm_inst(.CLKI(oscInternal), .CLKOP(clk), .CLKOS(clk90));
reg [63:0] wbuf;
always @(posedge clk) begin
wbuf <= wbuf + 1;//Fake logic
end
wire [31:0] sdram_dq_tx;
ODDRXE ODDRXE00_inst(.D0(wbuf[0]), .D1(wbuf[16]), .SCLK(clk90), .RST(1'b0), .Q(sdram_dq_tx[0]));
...
The design is very crowded and I get the following HOLD errors for all wbuf:
Error: The following path exceeds requirements by 1.585ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram_inst/wbuf[0] (from clkop +)
Destination: FF Data in sdram_inst/ODDRXE00_inst (to clkop2 +)
Delay: 0.380ns (34.5% logic, 65.5% route), 1 logic levels.
Constraint Details:
0.380ns physical path delay sdram_inst/SLICE_1029 to ddr_Dq[0]_MGIOL exceeds
-0.011ns DO_HLD and
0.000ns delay constraint less
-1.976ns skew less
0.000ns feedback compensation requirement (totaling 1.965ns) by 1.585ns
How could I constraint this path between the two clocks at 90° of each other in order to close the timing of my design? Would it make sense to force on wbuf a hold of 2ns (90° of 8ns) and how can I achieve that with a timing constraint?
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有些想法，虽然我不会声称它是答案，但作为答案发布比作为评论发布提供更好的结构；-)
两个上升沿之间只有 2 ns 可能太短，无法允许时序收敛，也是因为 wbuf Flip -Flops (FF) 位于主逻辑中，其中 DDR ODDRXE 位于 IO 边缘。
根据您在实际设计中可以执行的操作，有几种可能性：
Some ideas, though I will not claim it as answers, but posting as answer gives better structure than posting as comment ;-)
Having only 2 ns between the two rising edges is probably to short to allow for timing closure, also since the wbuf Flip-Flops (FFs) are in main logic, where the DDR ODDRXE is at the edge for IO.
Depending on what you can do in the actual design, there are several possibilities: