如何使用regs修改线路？
我对 Verilog 有点陌生，想知道如何修改电线。我知道你不能修改always块内的电线。
我见过类似的东西，您可以声明一些寄存器并将线路分配给这些寄存器（然后您可以修改寄存器来修改线路？）
module something
#(parameter D_W = 8)
(
input wire clk,
input wire rst,
output wire valid,
output wire [D_W-1:0] data,
);
reg valid_rg = 0;
reg [D_W-1:0] data_rg = 0;
assign valid = valid_rg;
assign data = data_rg;
我想知道如何对线路执行类似的操作，例如：
wire [7:0] wire_a [7:0];
最初我的我猜应该是这样的，
reg [7:0] wire_a_rg [7:0];
assign wire_a[7:0] = wire_a_rg[7:0];
但我有一种感觉，这可能是错误的。我该如何处理这个问题？
I am kind of new to Verilog and was wondering how I can modify wires. I know that you cannot modify wires inside always blocks.
I've seen something like this where you can declare some regs and assign the wire to those regs (which you can then modify the reg to modify the wire?)
module something
#(parameter D_W = 8)
(
input wire clk,
input wire rst,
output wire valid,
output wire [D_W-1:0] data,
);
reg valid_rg = 0;
reg [D_W-1:0] data_rg = 0;
assign valid = valid_rg;
assign data = data_rg;
I was wondering how to do something like that for a wire like:
wire [7:0] wire_a [7:0];
Initially my guess would be to have something like this
reg [7:0] wire_a_rg [7:0];
assign wire_a[7:0] = wire_a_rg[7:0];
But I have a feeling it might be wrong. How could I approach this?
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除非您需要对双向总线或具有多个驱动器的任何类型的电路进行建模，否则无需在 SystemVerilog 中使用连线。您可以编写
然后您可以在
always块中对valid/data进行程序分配，或者连续的分配声明（但不是两者）。顺便说一句，SystemVerilog 更喜欢使用
logic关键字而不是同义词reg。您应该阅读我关于网络和变量。
There's no need to use wires in SystemVerilog unless you need to model bi-directional buses, or any kind of circuitry with multiple drivers. You can write
And then you can make procedural assigmemnts to
valid/datain analwaysblock, or a continuousassignstatement (but not both).BTW, SystemVerilog prefers the use of
logickeyword over synonymreg.You should read my post about the difference between nets and variables.