是否有“信号”？暗示δ VHDL 延迟？

发布于 2025-01-07 08:07:42 字数 319 浏览 0 评论 0原文

你好，我想知道信号声明在 VHDL 中是如何工作的。由于它是内部信号，这是否意味着延迟？信号有内部存储器吗？示例：

Architecture SD_BEH of SD is
signal C: std_logic;
begin
 process (A)
  begin 
   C<=A;
   if (C='1') then B<=A;
   else B<= '0';
   end if;
  end process;
end SD_BEH;

C 的声明是否会引入 δ 延迟？如果是这样为什么？它是 VHDL 中的标准吗？谢谢。

原文

Hello i was wondering how a signal declaration really works in VHDL. Does it imply delay since its an internal signal? Do signals have an internal memory?
example:

Architecture SD_BEH of SD is
signal C: std_logic;
begin
 process (A)
  begin 
   C<=A;
   if (C='1') then B<=A;
   else B<= '0';
   end if;
  end process;
end SD_BEH;

Does this declaration of C introduce δ delay? If so why? Is it a standard in VHDL? Thanks.

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笑饮青盏花 2025-01-14 08:07:42

信号仅在增量周期结束时传播，因此您可以以某种方式将其称为具有“记忆”。将 VHDL 视为对真实硬件的描述，信号没有任何内存，除非对其进行建模，例如通过使用时钟进程来描述寄存器。

假设您上面的内容正在尝试对组合逻辑进行建模，它将无法正确模拟，因为敏感度列表不完整。需要明确的是，它会“正确”地模拟，因为它是根据 VHDL 语言规则编写的，但它不会描述任何类型的正常真实硬件。为了使其匹配，请考虑以下细微更改：

Architecture SD_BEH of SD is
signal C: std_logic;
begin
 process (A, C) -- add C to the sensitivity list
  begin 
   C<=A;
   if (C='1') then B<=A;
   else B<= '0';
   end if;
  end process;
end SD_BEH;

Signals only propagate at the end of a delta cycle, so you could call that having "memory" as in some manner. Viewing VHDL as a description for real hardware, signals do not have any memory unless they are modeled as such, for example by using a clocked process to describe a register.

Assuming what you have above is trying to model combinational logic, it won't simulate correctly, because the sensitivity list is not complete. To be clear, it will simulate "correctly" as it is written according to VHDL language rules, but it it won't describe any sort of normal real hardware. To make it match up, consider the following minor change:

Architecture SD_BEH of SD is
signal C: std_logic;
begin
 process (A, C) -- add C to the sensitivity list
  begin 
   C<=A;
   if (C='1') then B<=A;
   else B<= '0';
   end if;
  end process;
end SD_BEH;

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