在实现的 VHDL 代码中选择多路复用器的观点和事实。
好吧，在去年的数字设计课上，我们反复被告知，当给定许多不同的代码在结构上完成相同的事情时，编译器将如何实现或生成相同的结构。现在，在今年的计算机组织课上，我遇到了一种情况，想了解其他人的意见和知识。
据我了解，多路复用器的工作原理是，您将获得 x 个输入，并根据选择器信号输出这些输入之一。我理解，对于 8 个输入，您需要 N 个选择器位，以便 2^N=8。
有什么区别或优势吗？
entity myMultiplexer is
Port ( S0 : in STD_LOGIC_vector(0 to 1);
Sum : in STD_LOGIC;
myAnd : in STD_LOGIC;
myOr : in STD_LOGIC;
OpOut : out STD_LOGIC);
end myMultiplexer;
我的大问题是，让选择器说“其中 S0 是选择器”与让选择器像这样
entity myMultiplexer is
Port (
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
Sum : in STD_LOGIC;
myAnd : in STD_LOGIC;
myOr : in STD_LOGIC;
OpOut : out STD_LOGIC);
结束 myMultiplexer;
因此，在第一个中，在我看来，信号或电流将通过同一根电线进入，而在第二个中，信号或电流可能来自两个不同的东西。也许也是，我只是在想；您可以采用 2 个单独的输入并构造一个信号，告诉一个信号是矢量位 1，另一个信号是矢量位 0，然后将其发送到多路复用器 S0。
任何人对此的看法将不胜感激。
Ok, So in my digital design class last year we were told repeatedly how the compiler would realize or produce the same structure when given many different codes that did the same thing structurally. Now in my computer organization class this year I have came upon a situation and would like to gauge others opinion and knowledge.
As I understand a multiplexer to work you get x number of inputs and depending on a selector signal/s you output one of those inputs. I under stand that for say 8 inputs you want N number of selector bits so that 2^N=8.
My big question is, is there any difference or advantage of having the selector be say
entity myMultiplexer is
Port ( S0 : in STD_LOGIC_vector(0 to 1);
Sum : in STD_LOGIC;
myAnd : in STD_LOGIC;
myOr : in STD_LOGIC;
OpOut : out STD_LOGIC);
end myMultiplexer;
Where S0 is the selector as opposed to haveing the selector be like this
entity myMultiplexer is
Port (
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
Sum : in STD_LOGIC;
myAnd : in STD_LOGIC;
myOr : in STD_LOGIC;
OpOut : out STD_LOGIC);
end myMultiplexer;
So in the first one it would seem to me that the signal or electrical current would be coming in on the same wire where as with the second one you could have the source come from 2 separate things. Maybe also, i was just thinking; You could take 2 separate inputs and construct a signal telling one that it is vector bit 1 and the other it is vector bit 0 and then send that to the mux S0.
Anyones perspective on this would be appreciated.
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没有区别。第一个定义了一个包含两位的
信号。就你的问题而言，这仍然是两条“电线”。您的第一种风格更传统（正如我所见） - 因为如果需要，它更容易扩展到更多位。
No difference. The first one defines a single
signalwith two bits in it. In the terms of your question, this is still two "wires".You first style is more conventional (as I see it) - as it is easier to extend to more bits if required.