实时或时钟周期的门和开关延迟语句？
我一直在阅读不错的教程并且对第 55-56 页上的内容有一个简短的问题。我只需拖放下面的文本：
Gate and Switch delays
In real circuits, logic gates have delays associated with them. Verilog provides the
mechanism to associate delays with gates.
*Rise, fall and Turn-off delays
*Minimal, Typical, and Maximum delays.
Rise Delay
The rise delay is ... etc
Min value
The min value is the minimum delay value that the gate is expected to have.
Typ Value
... similar to min value
Max Value
... similar to min value
参考最小值（以及典型值和最大值）的解释，是否可以将最小值设置为多个时钟周期（因此是整数值）或实际的实际值（例如 10ns） ？我可以两者都做（选择其中之一）吗？
I've been reading through a nice tutorial and have a quick question concerning something on pages 55-56. I'll just drag and drop the text below:
Gate and Switch delays
In real circuits, logic gates have delays associated with them. Verilog provides the
mechanism to associate delays with gates.
*Rise, fall and Turn-off delays
*Minimal, Typical, and Maximum delays.
Rise Delay
The rise delay is ... etc
Min value
The min value is the minimum delay value that the gate is expected to have.
Typ Value
... similar to min value
Max Value
... similar to min value
Referring to the explanation for Min value (and Typ and Max alike), would one set the min value to a number of clock cycles (therefore integer value) or an actual real value like 10ns? Can I do both (choosing one or the other)?
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门和开关延迟是基于时间的，而不是基于周期的。例如，如果您的
timescale设置为1ns/1ns，并且您使用#10指定延迟，则您将获得 10ns 延迟。这些延迟对您创建的任何时钟信号一无所知。Gate and switch delays are time-based, not cycle based. For example, if your
timescaleis set to1ns/1ns, and you specify a delay using#10, you will get a 10ns delay. These delays know nothing about any clock signals you create.