解释堆栈、调用约定、寄存器、CPU 等内容的书籍或图形视频

发布于 2025-01-06 06:21:30 字数 180 浏览 7 评论 0原文

有没有一本书可以涵盖这一切……可悲的是我可以就所有这些事情进行肤浅的对话。我上过大学，所有这些科目都得了A，但我他妈的不明白堆栈或内存到底是什么样子。

我不“明白”线程到底是什么。 CPU 缓存行如何工作，以及它如何因读/写屏障而失效。像 TLB 之类的东西。

任何一本书或者一小部分可供阅读的书籍都会真正有帮助。

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从来不烧饼 2025-01-13 06:21:30

我假设您已经读过 Hennessy & 出版社的《计算机体系结构》。帕特森。但这可能无法回答您的问题。就我个人而言，虽然我是计算机体系结构方面的专家，但我并不是从任何地方学到的。事实上，我从 Ars Technica 和 Phoronix 的文章中学到了很多关于过去十年左右出现的每一个新架构的文章。

至于它们到底是什么样子，你需要学习芯片设计。您需要探索两个观点。一种是类似 CAD 的透视图，您可以在其中进行原理图捕获。您将逻辑块布局并连接在一起以形成数字电路。您所做的物理布局将大致对应于您在硬件中获得的布局。另一个角度是学习使用像 Verilog 这样的硬件描述语言进行编码，尽管这相当抽象，并且需要对硬件有很多直觉才能将您正在编码的内容与它将如何变成硬件相关联。

我在谷歌上搜索了“静态内存结构”的图像，发现了很多有趣的页面来展示内存是如何工作的。例如，这里有一些不错的图片“http://www.iis.ee.ethz.ch/~kgf/aries/5.html”。您稍后可以进入动态 RAM。静态 RAM 是由 6 个晶体管块组成的矩形阵列。请参阅“http://lwn.net/Articles/250967/”，特别是“http://lwn.net/images/cpumemory/cpumemory.7.png”。另外，“http://www.freepatentsonline.com/7095663-0-large.jpg”。其中四个晶体管形成两个背靠背反相器，保存一个位值。其中两个允许访问逆变器之间的信号线，从而允许您强制它们进入不同的状态。这些 6T 单元排列成大的矩形阵列。为了读取一行，解码器电路将地址转换为单个信号并断言该行的字线，这激活存取晶体管，将该行中的每个单元连接到其位线。每列的两条位线保存相反的值，这些值由差分读出放大器解释，并且您读出一行。要写入，您可以执行相同的操作，但强制位线为正确的值。

堆栈只是以特定方式寻址的内存。即使在芯片中专门专用的堆栈结构中，它们也只是内存块，以及适当递增和递减地址的逻辑块。

高速缓存是另一种通用存储器阵列，与标签阵列相关联，标签阵列是一种特殊类型的内容可寻址存储器。 TLB 是一种特殊的缓存。花一些时间谷歌搜索，您可以了解所有这些内容。您必须克服的障碍是知道要使用哪些搜索词。我很乐意为此提供帮助。

I'm assuming you've read "Computer Architecture" by Hennessy & Patterson. But that may not answer your questions. Personally, although I'm an expert in computer architecture, I didn't learn it from any one place. In fact, I learned a lot from reading Ars Technica and Phoronix articles about every new architecture that came out in the past decade or so.

As for what they REALLY look like, you'll need to learn chip design. There are two viewpoints you'll want to explore. One is a CAD-like perspective, where you do schematic capture. You lay out and connect logic blocks together to form digital circuits. The physical layout you make will correspond roughly to the layout you get in hardware. The other angle is to learn to code in a hardware description language like Verilog, although that's rather abstract, and it requires a lot of intuition about the hardware to relate what you're coding to how it's going to turn into hardware.

I googled for images of "static ram structure", and I found lots of interesting pages that demonstrate how memories work. There are some good images here "http://www.iis.ee.ethz.ch/~kgf/aries/5.html" for instance. You can get into dynamic RAMs later. A static RAM is a rectangular array of 6-transistor blocks. See "http://lwn.net/Articles/250967/" and specifically "http://lwn.net/images/cpumemory/cpumemory.7.png". Also, "http://www.freepatentsonline.com/7095663-0-large.jpg". Four of the transistors form two back-to-back inverters, holding a bit value. Two allow access to the signal lines between the inverters, allowing you to coerce them into a different state. These 6T cells are arranged in large rectangular arrays. To read a row, a decoder circuit translates an address into a single signal and asserts that row's word line, which activates the access transistors, connecting each cell in that row to its bit lines. The two bit lines for each column hold opposite values, which are interpreted by differential sense amplifiers, and you're read out a row. To write, you do the same but force the bit lines to the correct values.

A stack is just memory addressed in a particular way. Even in specially-dedicated stack structures in chips, they're just memory blocks, along with a logic block that increments and decrements an address appropriately.

A cache is another generic memory array, associate with a tag array, which is a particular kind of content addressable memory. A TLB is a special kind of cache. Spending some time googling, you can learn all about these things. The hurdle you have to get over is knowing what search terms to use. I'm happy to help with that.

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