Wikipedia answers this question well in its entry "Logic synthesis".
The synopsis is that synthesis transforms high level verilog/vhdl constructs, which don't have real physical hardware that can be wired up to do your logic, into low level logical constructs which can be literally modeled in the form of transistor logic or look-up tables or other FPGA or ASIC hardware components.
Verilog is both a scripting language and a HDL (hardware description language). The scripting component is often used to write testbenches to verify the HDL or (in limited cases) as a metaprogramming language to generate HDL from input parameters. One thing that confuses newcomers is that almost every Verilog tutorial starts out teaching you about the scripting parts of the language. It can act like a simple, imperative, sequential programming language. You can do loops and print results. Almost all of that is irrelevant when you are restricted to the synthesizable subset of Verilog which can be used as an HDL. If someone asks you if you've done Verilog synthesis they are probably trying to distinguish whether you have taken any Verilog designs all the way to actual hardware. Having done so would demonstrate that you understand how to use Verilog as an HDL. If you have only done simulation you may be relying on language features that are not synthesizable and thus not usable in real hardware.
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维基百科在其条目“逻辑综合”中很好地回答了这个问题。
概要是，综合将高级 verilog/vhdl 构造（没有可以连接来执行逻辑的实际物理硬件）转换为低级逻辑构造，这些构造可以在晶体管逻辑或查找表或其他FPGA或ASIC硬件组件的形式。
Wikipedia answers this question well in its entry "Logic synthesis".
The synopsis is that synthesis transforms high level verilog/vhdl constructs, which don't have real physical hardware that can be wired up to do your logic, into low level logical constructs which can be literally modeled in the form of transistor logic or look-up tables or other FPGA or ASIC hardware components.
Verilog 既是一种脚本语言，也是一种 HDL（硬件描述语言）。脚本组件通常用于编写测试平台来验证 HDL，或者（在有限的情况下）作为元编程语言从输入参数生成 HDL。让新手感到困惑的一件事是，几乎每个 Verilog 教程都是从教您该语言的脚本部分开始的。它可以像一种简单、命令式、顺序编程语言一样工作。您可以执行循环并打印结果。当您仅限于可用作 HDL 的 Verilog 的可综合子集时，几乎所有这些都是无关紧要的。如果有人问您是否完成了 Verilog 综合，他们可能会试图区分您是否将任何 Verilog 设计一直采用到实际硬件。这样做将证明您了解如何使用 Verilog 作为 HDL。如果您只进行了模拟，您可能依赖于不可综合的语言功能，因此无法在真实硬件中使用。
Verilog is both a scripting language and a HDL (hardware description language). The scripting component is often used to write testbenches to verify the HDL or (in limited cases) as a metaprogramming language to generate HDL from input parameters. One thing that confuses newcomers is that almost every Verilog tutorial starts out teaching you about the scripting parts of the language. It can act like a simple, imperative, sequential programming language. You can do loops and print results. Almost all of that is irrelevant when you are restricted to the synthesizable subset of Verilog which can be used as an HDL. If someone asks you if you've done Verilog synthesis they are probably trying to distinguish whether you have taken any Verilog designs all the way to actual hardware. Having done so would demonstrate that you understand how to use Verilog as an HDL. If you have only done simulation you may be relying on language features that are not synthesizable and thus not usable in real hardware.