MIPS 同步（ll/sc）
我想知道如果在使用 ll/sc 时在执行 sc 语句之前处理器发生变化，会产生什么结果。
例如
CPU 1 ==> $t1 = 1, $t0 = 2
CPU 2 ==> $t1 = 30, $t0 = 40
内存 ==> $s0 = 99
如果我们执行这些语句：
ll $t1, 0($s0) # CPU 1
ll $t1, 0($s0) # CPU 2
addi $t1, $t1, 1 # CPU 2
sc $t1, 0($s0) # CPU 2 ($t1 = 1, $s0 = 100)
sc $t0, 0($s0) # CPU 1
我知道执行后（如果我错了请纠正我）：
CPU 2 ==> $t1 = 1, $t0 = 40
CPU 1 ==> $t1 = 99
我不知道在最后一个 CPU 1 命令之后 $s0 和 $t0 会发生什么。 $s0 = 2 吗？
I wanted to know that if while using ll/sc there is a change in processor before the sc statement is executed what would be result.
E.g.
CPU 1 ==> $t1 = 1, $t0 = 2
CPU 2 ==> $t1 = 30, $t0 = 40
MEMORY ==> $s0 = 99
If we execute these statements:
ll $t1, 0($s0) # CPU 1
ll $t1, 0($s0) # CPU 2
addi $t1, $t1, 1 # CPU 2
sc $t1, 0($s0) # CPU 2 ($t1 = 1, $s0 = 100)
sc $t0, 0($s0) # CPU 1
I know that after the execution (Correct me if I am wrong):
CPU 2 ==> $t1 = 1, $t0 = 40
CPU 1 ==> $t1 = 99
I don't know what will happen to $s0 and $t0 after the last CPU 1 command. Will $s0 = 2 ??
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好吧...我自己找到了解决方案...由于从首次在 CPU1 上执行 ll 语句时 CPU 发生了变化，并且 CPU2 正在修改相同的内存区域，因此第 5 行（最后一行）中的 sc 会失败。所以当 sc 失败时 $t0 = 0 &由于最后一行中的 sc 故障导致内存未被修改，因此 $s0 = 100
来源：http://www.weblearn.hs-bremen.de/risse/RST/docs/MIPS/mips-isa.pdf
读取加载链接 (LL) 和条件存储(SC) 提取物。
Alright...I found the solution myself... As there has been a change in CPU from when the ll statement was first executed on CPU1 and that CPU2 is modifying the same memory region, so sc in line 5 (last line) would fail. So when sc fails $t0 = 0 & as memory is not modified due to sc failure in last line so $s0 = 100
Source: http://www.weblearn.hs-bremen.de/risse/RST/docs/MIPS/mips-isa.pdf
Read Load Linked (LL) and Store Conditional (SC) extracts.