MIPS 组装特性
我正在尝试编译 MIPS 架构特性的列表，到目前为止，
- 由于
- 加载延迟导致的分支延迟，导致乱序执行，
我是否忽略了在读取 MIPS 程序集时可能让我失望的任何内容上市？我的背景只有Intel/i386）。
I'm trying to compile a list of MIPS architecture peculiarities, and so far has come up with
- out of order execution due to branch delay
- out of order execution due to load delay
Am I overlooking anything that could throw me off when reading a MIPS assembly listing? My background is only Intel/i386).
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MIPS 比 x86 所能梦想的更加正交。几乎每条指令都可以使用任何输入和输出寄存器来完成，并且通常只需要 1 个周期 - 并且很容易看出哪里不需要。除此之外，他们使用 Load 作为 pnumonic 而不是 Move，并且有一个更直接的寻址系统（再见 word ptr），但我称之为所有上述优点。你提到的无序的事情是我能想到的唯一出乎意料的问题。
MIPS is much more orthogonal than x86 could ever dream of being. Just about every instruction can be done with any input and output register and usually only takes 1 cycle - and where it doesn't it is easy to tell. Beyond that, they use Load as a pnumonic instead of Move and have a more straight forward addressing system (bye bye word ptr), but I call all of the above advantages. The out of order things you've mentioned are the only things I can think of in terms of gotchas that are way unexpected.