如何在 VHDL 中声明具有多个零的输出

发布于 2024-12-29 00:59:25 字数 587 浏览 2 评论 0原文

您好，我正在尝试找到一种方法来替换此命令： Bus_S <= "0000000000000000000000000000000" & Ne; 有更方便的东西。一位一位地计算零并不是很复杂。该程序是关于 ALU（以 mips 为单位）的 SLT 单元。 SLT 仅获取 1 位（ADDSU32 的 MSB），并具有 32 位全零输出，但第一位取决于 ADDSU32 的 Ne=MSB。（请暂时忽略ALUop）

entity SLT_32x is
   Port ( Ne : in  STD_LOGIC;
         ALUop : in STD_LOGIC_VECTOR (1 downto 0);
         Bus_S : out  STD_LOGIC_VECTOR (31 downto 0));
end SLT_32x;

architecture Behavioral of SLT_32x is
begin
  Bus_S <= "0000000000000000000000000000000" & Ne; 
end Behavioral;

有没有办法使用（30 downto 0）='0'或类似的东西？谢谢。

原文

Hello i am trying to find a way to replace this command: Bus_S <= "0000000000000000000000000000000" & Ne; with something more convenient. Counting zeros one by one is not very sophisticated. The program is about an SLT unit for an ALU in mips. The SLT gets only 1 bit(MSB of an ADDSU32) and has an output of 32 bits all zeros but the first bit that depends on the Ne=MSB of ADDSU32. (plz ignore ALUop for the time being)

entity SLT_32x is
   Port ( Ne : in  STD_LOGIC;
         ALUop : in STD_LOGIC_VECTOR (1 downto 0);
         Bus_S : out  STD_LOGIC_VECTOR (31 downto 0));
end SLT_32x;

architecture Behavioral of SLT_32x is
begin
  Bus_S <= "0000000000000000000000000000000" & Ne; 
end Behavioral;

Is there a way to use (30 downto 0)='0' or something like that? Thanks.

分享到QQ

分享到微博

如果你对这篇内容有疑问，欢迎到本站社区发帖提问参与讨论，获取更多帮助，或者扫码二维码加入 Web 技术交流群。

发布评论

需要登录才能够评论，你可以免费注册一个本站的账号。

筑梦 2025-01-05 00:59:25

试试这个：bus_S <= (0 => Ne, other => '0')
意思是：将第0位设置为Ne，并将其他位设置为“0”。

回复收藏 0 原文

暗地喜欢 2025-01-05 00:59:25

给定答案的替代方案：

architecture Behavioral of SLT_32x is
begin
  Bus_S <= (others => '0');
  Bus_S(0) <= ne;
end Behavioral;

始终考虑组合过程中的最后一个分配。当对大多数情况进行默认分配并随后添加特殊情况时，这使得代码非常可读，即通过分层块馈送宽总线（定义为记录）并仅修改一些信号。

alternative to the given answers:

architecture Behavioral of SLT_32x is
begin
  Bus_S <= (others => '0');
  Bus_S(0) <= ne;
end Behavioral;

Always the last assignment in a combinatoric process is taken into account. This makes very readable code when having a default assignment for most of the cases and afterwards adding the special cases, i.e. feeding a wide bus (defined as record) through a hierarchical block and just modifying some of the signals.

回复收藏 0 原文

~没有更多了~